公开(公告)号：US20030234413A1

公开(公告)日：2003-12-25

申请号：US10414252

申请日：2003-04-14

Applicant: STMicroelectronics S.r.I.

Inventor： Giampiero Sberno ,  Salvatore Torrisi ,  Nicolas Demange

IPC: H01L029/76

CPC classification number: G11C7/18 ,  G11C11/22 ,  G11C2211/4013

Abstract: A ferroelectric semiconductor memory includes an arrangement of memory units comprising at least one row of memory units. The memory units of the at least one row are associated with a respective word line of the arrangement. The arrangement of memory unit includes a plurality of local word lines branching off from the word line associated with the at least one row, each local word line being connected to a respective group of memory units of the line. Selective connection means allow to selectively connect one of the local word lines to the respective word line. The arrangement of memory units further includes a plurality of local plate biasing lines, each one associated with the memory units of a respective group of memory units, for selectively driving the memory units of the respective groups.

Abstract translation: 铁电半导体存储器包括包括至少一行存储器单元的存储器单元的布置。 至少一行的存储器单元与该布置的相应字线相关联。 存储单元的布置包括从与至少一行相关联的字线分支的多个本地字线，每个本地字线连接到线路的相应组的存储器单元。 选择性连接装置允许选择性地将本地字线之一连接到相应的字线。 存储单元的布置还包括多个局部板偏置线，每个板偏置线与相应组的存储单元相关联，用于选择性地驱动各组的存储单元。