公开(公告)号：US11595039B2

公开(公告)日：2023-02-28

申请号：US17658016

申请日：2022-04-05

Applicant: STMicroelectronics S.r.I.

Inventor： Noemi Gallo ,  Edoardo Botti

IPC: H03K17/00 ,  H03K17/56 ,  H03K19/20 ,  H03K17/687

Abstract: A circuit includes a high-side switch and a low-side switch. A first inverter includes first and second discharge current paths activatable to sink first and second discharge currents, respectively, from the control terminal of the high-side switch. A second inverter includes first and second charge current paths activatable to source first and second charge currents to the control terminal of the low-side switch. A high-side sensing current path includes an intermediate high-side control node, and a low-side sensing current path includes an intermediate low-side control node. The second discharge current path is selectively enablable in response to a high-side detection signal at the intermediate high-side control node having a high logic value, and the second charge current path is selectively enablable in response to a low-side detection signal at the intermediate low-side control node having a low logic value.

公开(公告)号：US20220337236A1

公开(公告)日：2022-10-20

申请号：US17658016

申请日：2022-04-05

Applicant: STMicroelectronics S.r.I.

Inventor： Noemi Gallo ,  Edoardo Botti

IPC: H03K17/56 ,  H03K19/20

Abstract: A circuit includes a high-side switch and a low-side switch. A first inverter includes first and second discharge current paths activatable to sink first and second discharge currents, respectively, from the control terminal of the high-side switch. A second inverter includes first and second charge current paths activatable to source first and second charge currents to the control terminal of the low-side switch. A high-side sensing current path includes an intermediate high-side control node, and a low-side sensing current path includes an intermediate low-side control node. The second discharge current path is selectively enablable in response to a high-side detection signal at the intermediate high-side control node having a high logic value, and the second charge current path is selectively enablable in response to a low-side detection signal at the intermediate low-side control node having a low logic value.