公开(公告)号：US20040217896A1

公开(公告)日：2004-11-04

申请号：US10764133

申请日：2004-01-23

Applicant: STMicroelectronics S.r.l

Inventor： Giovanni Cesura ,  Andrea Panigada ,  Alessandro Bosi

IPC: H03M001/38

CPC classification number: H03M1/0641 ,  H03M1/167

Abstract: An analog-to-digital converter (200) with a pipeline architecture for converting an analog input signal into a digital output signal with a predefined resolution is proposed. The converter includes a plurality of stages (1053-1050) each one having means (110, 115) for converting an analog local signal into a digital local signal with a local resolution lower than said resolution, means (120, 125) for determining an analog residue indicative of a quantization error of the means for converting, and means (130) for amplifying the analog residue by an inter-stage gain corresponding to the local resolution to generate the analog local signal for a next stage, and further includes means (204) for combining the digital local signals of all the stages into the digital output signal weighting each digital local signal according to a digital weight depending on the corresponding inter-stage gain. In the converter of the invention, the means for combining includes, for at least one of the stages (1053), means (205-240) for dynamically estimating a digital correction signal indicative of an analog error of the corresponding inter-stage gain, and means (230) for controlling the digital weight according to the digital correction signal.

Abstract translation: 提出了具有用于将模拟输入信号转换成具有预定分辨率的数字输出信号的流水线架构的模数转换器（200）。 所述转换器包括多个级（1053-1050），每个级具有用于将模拟本地信号转换成具有低于所述分辨率的局部分辨率的数字本地信号的装置（110,115），用于确定 表示用于转换的装置的量化误差的模拟残留以及用于通过对应于局部分辨率的级间增益来放大模拟残差的装置（130），以产生下一级的模拟本地信号，并且还包括装置 204），用于将所有级的数字本地信号组合成数字输出信号，根据相应的级间增益，根据数字权重对每个数字本地信号进行加权。 在本发明的转换器中，用于组合的装置包括用于动态估计指示相应级间增益的模拟误差的数字校正信号的装置（205-240）中的至少一个级（1053） 以及用于根据数字校正信号控制数字权重的装置（230）。