公开(公告)号：US20180205389A1

公开(公告)日：2018-07-19

申请号：US15711776

申请日：2017-09-21

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： CHIH-LUNG CHEN ,  CHI-YING LEE ,  KUO-SHENG CHUNG ,  SHIH-HSIUNG HUANG

IPC: H03M1/16 ,  H03M1/74

CPC classification number: H03M1/167 ,  H03M1/0695 ,  H03M1/361 ,  H03M1/74 ,  H03M1/804

Abstract: A pipelined analog-to-digital converter (ADC) and an operating method are provided. The pipelined ADC includes a multiplying digital-to-analog converter (MDAC) and a sub-ADC. The MDAC alternatively operates in an amplifying phase and a sampling phase according to two non-overlapping clocks, and performs operations on an input signal in the amplifying phase according to a target voltage determined by a digital code. The sub ADC includes multiple comparators, a determination circuit, and an encoding circuit. The comparators generate multiple comparison results by comparing the input signal with multiple predetermined voltages. The determination circuit generates multiple comparison completion signals in a non-overlapping interval of the two clocks according to the comparison results. The comparison completion signals respectively indicate whether the comparators complete the comparison. The encoding circuit determines the digital code according to the comparison results and the comparison completion signals.

公开(公告)号：US09432045B2

公开(公告)日：2016-08-30

申请号：US14524729

申请日：2014-10-27

Applicant: ANALOG DEVICES GLOBAL

Inventor： Hajime Shibata

IPC: H03M1/38 ,  H03M1/44 ,  H03M1/12 ,  H03M1/00 ,  H03M1/16

CPC classification number: H03M1/44 ,  H03M1/001 ,  H03M1/002 ,  H03M1/124 ,  H03M1/1245 ,  H03M1/167

Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

Abstract translation: A转换器可以包括串联连接的多个转换器级。 每个转换器级可以接收时钟信号和模拟输入信号，并且可以产生模拟输出信号和数字输出信号。 每个转换器级可以包括产生数字输出信号的编码器，产生重构信号的解码器，产生延迟信号的延迟转换器和产生残差信号的放大器，其中延迟信号可以是连续电流信号。

公开(公告)号：US09136852B2

公开(公告)日：2015-09-15

申请号：US14366254

申请日：2013-02-22

Applicant: Qixing Chen ,  Qiyu Luo

Inventor： Qixing Chen ,  Qiyu Luo

IPC: H03M1/00 ,  H03M1/16 ,  H03M1/68 ,  H03M1/76

CPC classification number: H03M1/001 ,  H03M1/167 ,  H03M1/682 ,  H03M1/765

Abstract: Multi-stage parallel super-high-speed ADC and DAC of a logarithmic companding law has a voltage follower switch having zero voltage drop, and also has a lossless threshold switch group, wherein a quantization voltage of A/D conversion or D/A conversion is directly obtained through voltage-dividing resistance thereof. The ADC and DAC simplify a conversion process and reduce a conversion error. The ADC and DAC provide multi-stage multi-bit parallel super-high-speed A/D conversion and D/A conversion with logarithmic companding law of a high conversion rate and the low conversion error.

公开(公告)号：US20150236709A1

公开(公告)日：2015-08-20

申请号：US14183159

申请日：2014-02-18

Applicant: Stéphane BOUVIER ,  Sylvain Dumont ,  Luis Rolindez

Inventor： Stéphane BOUVIER ,  Sylvain Dumont ,  Luis Rolindez

IPC: H03M1/10 ,  H03M1/36 ,  H03M1/46 ,  H03M1/12

CPC classification number: H03M1/181 ,  H03M1/167 ,  H03M1/365

Abstract: Systems and methods for protecting an analog-to-digital converter (ADC) are provided. The provided systems and methods utilize comparators in a circuit of a stage of the ADC to compare a reference signal to an input signal and output one or more maximum signals when the input signal exceeds the reference signal. A decoder in the stage of the ADC may output a reset signal to another circuit in the stage of the ADC when a predetermined number of the maximum signals are received. When the other circuit receives the reset signal, the ADC may enter a protection mode to protect the ADC by ensuring that the excessive input signal is not propagated to subsequent stages.

Abstract translation: 提供了用于保护模数转换器（ADC）的系统和方法。 所提供的系统和方法利用ADC级的电路中的比较器将参考信号与输入信号进行比较，并在输入信号超过参考信号时输出一个或多个最大信号。 当接收到预定数量的最大信号时，ADC阶段的解码器可以在ADC的阶段将复位信号输出到另一个电路。 当另一个电路接收到复位信号时，ADC可能进入保护模式以保护ADC，以确保过多的输入信号不会传播到后续级。

公开(公告)号：US08742961B2

公开(公告)日：2014-06-03

申请号：US13742212

申请日：2013-01-15

Applicant: Synopsys, Inc.

Inventor： Pedro Miguel Ferreira de Figueiredo ,  Gonçalo Manuel Tordo Minderico ,  Carlos Pedro dos Santos Fachada

IPC: H03M1/06

CPC classification number: H03M1/1009 ,  H03M1/06 ,  H03M1/1061 ,  H03M1/167

Abstract: A switching scheme is used during a calibration mode for determining calibration coefficients of each calibrated stage of a pipeline analog-to-digital converter (ADC). A calibrated stage of the pipeline ADC includes an amplifier for amplifying a residue voltage of the stage and a sampling capacitor comprising a plurality of sub-capacitors. The plurality of sub-capacitors have a first terminal connected to an input of amplifier and a second terminal connected to one or more switches that selectively couple the second terminal to the input terminal of the stage, a first reference voltage or a second reference voltage lower than the first reference voltage. During foreground calibration, a number of measurements are taken at an output of the amplifier to determine the calibration coefficient of the calibrated stage.

Abstract translation: 在校准模式期间使用切换方案来确定管线模数转换器（ADC）的每个校准级的校准系数。 流水线ADC的校准级包括用于放大级的残余电压的放大器和包括多个子电容器的采样电容器。 多个子电容器具有连接到放大器的输入的第一端子和连接到选择性地将第二端子耦合到级的输入端子的一个或多个开关的第二端子，第一参考电压或第二参考电压较低 比第一个参考电压。 在前景校准期间，在放大器的输出处进行多次测量以确定校准级的校准系数。

公开(公告)号：US08730073B1

公开(公告)日：2014-05-20

申请号：US13738557

申请日：2013-01-10

Applicant: Broadcom Corporation

Inventor： Tao Wang ,  Chun-Ying Chen ,  Jiangfeng Wu

IPC: H03M1/00

CPC classification number: H03M1/1215 ,  H03M1/167

Abstract: A method for digitizing an analog signal through a pipelined analog-to-digital converter (ADC) may include pipelining a sample sub-stage, a quantization sub-stage and an amplification sub-stage to an ADC lane. Within a first of multiple pipelined stages, clock phases may be assigned to the ADC lane, including a sample clock phase, a quantization clock phase, and an amplification clock phase such that the quantization clock phase is non-overlapping with the sample clock phase and the amplification clock phase. The non-overlapping feature may be facilitated by generating multiple reference clock phases for the sub-stages of multiple ADC lanes, and interleaving assignment of the sample clock phase, the quantization clock phase, and the amplification clock phase to the reference clock phases among the multiple lanes.

Abstract translation: 通过流水线模数转换器（ADC）对模拟信号进行数字化的方法可以包括将样本子级，量子化级和放大级分别流水线到ADC通道。 在多个流水线阶段的第一阶段中，可以将时钟相位分配给ADC通道，包括采样时钟相位，量化时钟相位和放大时钟相位，使得量化时钟相位与采样时钟相位不重叠， 放大时钟相位。 可以通过为多个ADC通道的子级产生多个参考时钟相位并且将采样时钟相位，量化时钟相位和放大时钟相位的分配交织到参考时钟相位中，从而促进非重叠特征 多条车道。

公开(公告)号：US08692701B2

公开(公告)日：2014-04-08

申请号：US13599195

申请日：2012-08-30

Applicant: Shoji Kawahito ,  Sung Wook Jung ,  Osamu Kobayashi ,  Yasuhide Shimizu ,  Takahiro Miki ,  Takashi Morie ,  Hirotomo Ishii

Inventor： Shoji Kawahito ,  Sung Wook Jung ,  Osamu Kobayashi ,  Yasuhide Shimizu ,  Takahiro Miki ,  Takashi Morie ,  Hirotomo Ishii

IPC: H03M1/38

CPC classification number: H03M1/06 ,  H03M1/167

Abstract: A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.

Abstract translation: 流水线A / D转换器电路包括：采样保持电路，被配置为采样和保持模拟输入信号，并输出采样保持信号;以及A / D转换器电路，包括级联地彼此连接的A / D转换器电路部分， 并以流水线形式执行A / D转换。 每级的流水线A / D转换器电路部分包括子A / D转换器电路，乘法器D / A转换器电路和预充电电路。 子A / D转换电路包括比较器，A / D将输入信号转换为预定位的数字信号; D / A转换器电路，用于对来自子A / D转换器的数字信号进行D / A转换 电路作为参考电压产生的模拟控制信号作为参考值，通过基于模拟控制信号的采样电容进行采样，保持和放大输入信号。

公开(公告)号：US08547257B2

公开(公告)日：2013-10-01

申请号：US13282262

申请日：2011-10-26

Applicant: John Earle Miller ,  Robert Floyd Payne

Inventor： John Earle Miller ,  Robert Floyd Payne

IPC: H03M1/06

CPC classification number: H03M1/0687 ,  H03M1/167

Abstract: An analog-to-digital converter (ADC) function in which digital error correction is provided. Parallel ADC stages are synchronously clocked to convert an analog input signal into digital words; at least one of the digital outputs is encoded according to an error correction code. Decision logic circuitry decodes a code word comprised of the concatenation of the digital outputs from the parallel stages, to derive a digital output from which the digital output word corresponding to the analog input signal can be derived. The decision logic circuitry can provide an error signal used to correct the state of one or more bits of the digital output from one of the ADC stages, for the case of a systematic code; alternatively, the decision logic circuitry can directly decode the code word to provide the digital output. The architecture may be applied to stages in a pipelined ADC.

Abstract translation: 提供数字纠错的模数转换器（ADC）功能。 并行ADC级同步计时，将模拟输入信号转换为数字字; 数字输出中的至少一个根据纠错码进行编码。 判决逻辑电路对包括来自并行级的数字输出的组合的代码字进行解码，以导出数字输出，从该数字输出可以导出与模拟输入信号对应的数字输出字。 对于系统代码的情况，判决逻辑电路可以提供用于校正来自ADC级之一的数字输出的一个或多个位的状态的误差信号; 或者，判决逻辑电路可以直接解码码字以提供数字输出。 该架构可以应用于流水线ADC中的阶段。

公开(公告)号：US08525712B2

公开(公告)日：2013-09-03

申请号：US13195144

申请日：2011-08-01

Applicant: Takashi Oshima ,  Tatsuji Matsuura ,  Naoki Yada ,  Takahiro Miki ,  Akihiro Kitagawa ,  Tetsuo Matsui ,  Kunihiko Usui

Inventor： Takashi Oshima ,  Tatsuji Matsuura ,  Naoki Yada ,  Takahiro Miki ,  Akihiro Kitagawa ,  Tetsuo Matsui ,  Kunihiko Usui

IPC: H03M1/10

CPC classification number: H03M1/1033 ,  G01S7/4021 ,  G01S13/931 ,  H03M1/167 ,  H03M1/442

Abstract: To improve resolution of a built-in A/D converter by reducing the area occupied by a chip of the built-in A/D converter in a semiconductor integrated circuit that is mounted in an on-vehicle millimeter wave radar device and which incorporates an A/D converter and an MPU. In the semiconductor integrated circuit, a plurality of reception signals of the radar device is A/D-converted by a single digital correction type A/D converter. The digital correction type A/D converter of the single A/D converter is a foreground digital correction type A/D converter that sequentially A/D-converts the reception signals output from a multiplexer of a receiving interface. The single A/D converter includes a pipeline type A/D converter having a plurality of cascade-coupled converters. The semiconductor integrated circuit comprises a correction signal generating unit, a digital correction D/A converter, and a digital correction unit for digital correction.

Abstract translation: 通过在安装在车载毫米波雷达装置中的半导体集成电路中减小内置A / D转换器的芯片所占用的面积来提高内置A / D转换器的分辨率， A / D转换器和MPU。 在半导体集成电路中，由单个数字校正型A / D转换器对雷达装置的多个接收信号进行A / D转换。 单个A / D转换器的数字校正型A / D转换器是从接收接口的多路复用器输出的接收信号顺序进行A / D转换的前景数字校正型A / D转换器。 单个A / D转换器包括具有多个级联耦合转换器的流水线型A / D转换器。 半导体集成电路包括校正信号生成单元，数字校正D / A转换器和用于数字校正的数字校正单元。

公开(公告)号：US20130187801A1

公开(公告)日：2013-07-25

申请号：US13742212

申请日：2013-01-15

Applicant: Synopsys, Inc.

Inventor： Pedro Miguel Ferreira de Figueiredo ,  Gonçalo Manuel Tordo Minderico ,  Carlos Pedro dos Santos Fachada

IPC: H03M1/10 ,  H03M1/06

CPC classification number: H03M1/1009 ,  H03M1/06 ,  H03M1/1061 ,  H03M1/167

Abstract: A switching scheme is used during a calibration mode for determining calibration coefficients of each calibrated stage of a pipeline analog-to-digital converter (ADC). A calibrated stage of the pipeline ADC includes an amplifier for amplifying a residue voltage of the stage and a sampling capacitor comprising a plurality of sub-capacitors. The plurality of sub-capacitors have a first terminal connected to an input of amplifier and a second terminal connected to one or more switches that selectively couple the second terminal to the input terminal of the stage, a first reference voltage or a second reference voltage lower than the first reference voltage. During foreground calibration, a number of measurements are taken at an output of the amplifier to determine the calibration coefficient of the calibrated stage.

Abstract translation: 在校准模式期间使用切换方案来确定管线模数转换器（ADC）的每个校准级的校准系数。 流水线ADC的校准级包括用于放大级的残余电压的放大器和包括多个子电容器的采样电容器。 多个子电容器具有连接到放大器的输入的第一端子和连接到选择性地将第二端子耦合到级的输入端子的一个或多个开关的第二端子，第一参考电压或第二参考电压较低 比第一个参考电压。 在前景校准期间，在放大器的输出处进行多次测量以确定校准级的校准系数。