公开(公告)号：US20040173869A1

公开(公告)日：2004-09-09

申请号：US10713538

申请日：2003-11-14

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto Bez ,  Alessandro Grossi

IPC: H01L029/00

CPC classification number: H01L21/76232 ,  H01L21/76229 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11531

Abstract: A process for self-aligned manufacturing of integrated electronic devices includes: forming, in a semiconductor wafer having a substrate, insulation structures that delimit active areas and project from the substrate; forming a first conductive layer, which coats the insulation structures and the active areas; and partially removing the first conductive layer. In addition, recesses are formed in the insulation structures before forming said first conductive layer.

Abstract translation: 一种用于集成电子器件的自对准制造的方法包括：在具有衬底的半导体晶片中形成限定有源区并从衬底突出的绝缘结构; 形成第一导电层，其涂覆绝缘结构和有源区; 并部分地去除第一导电层。 此外，在形成所述第一导电层之前，在绝缘结构中形成凹部。