公开(公告)号：US10715143B1

公开(公告)日：2020-07-14

申请号：US16271474

申请日：2019-02-08

Applicant: STMicroelectronics S.r.l.

Inventor： Agatino Antonino Alessandro ,  Carmelo Ardizzone

IPC: H03K19/003 ,  H03K19/007

Abstract: Disclosed herein is a circuit including first and second input circuits. The first input circuit is configured to receive first and second logic signals and to source current to first and second control nodes if at least one of the first and second logic signals is at a logic low. The second input circuit is configured to receive the first and second logic signals and to sink current from the first and second control nodes if at least one of the first and second logic signals is at a logic high. A first output circuit is configured to source current to an output node when current is sunk from the first control node. A second output circuit is configured to sink current from the output node when current is sourced to the second control node. A latch is coupled to the output node.