公开(公告)号：US20230318589A1

公开(公告)日：2023-10-05

申请号：US18127397

申请日：2023-03-28

申请人： STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

发明人： Giulio ZOPPI ,  Vincent Pascal ONDE ,  Giuseppe ROMANO

IPC分类号： H03K5/1254 ,  G01D5/347 ,  H03K3/013

CPC分类号： H03K5/1254 ,  G01D5/3473 ,  H03K3/013

摘要： A first input node receives a first input signal and a second input node receives a second input signal. The first and second input signals are in phase quadrature. An edge detector circuit senses the first input signal and produces a pulsed signal indicative of edges detected in the first input signal. A pulse skip and reset circuit senses the pulsed signal and the second input signal, and produces a reset signal indicative of pulses detected in the pulsed signal while the second input signal is de-asserted. A sampling circuit senses the second input signal and the reset signal, and produces an output signal that is deasserted in response to assertion of the second input signal and is asserted in response to a pulse being detected in the reset signal.