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公开(公告)号：US11906994B2
公开(公告)日：2024-02-20
申请号：US17836524
申请日：2022-06-09
Inventor： Daniele Mangano , Andrei Tudose , Francesco Clerici , Pasquale Butta'
IPC: G06F1/00 , G05F1/46 , G06F1/3296
CPC classification number: G05F1/468 , G06F1/3296
Abstract: A voltage regulator is embedded in a circuit intermediate a first node (coupled to a battery) and a second node (supplying power to an external memory). The voltage regulator is activatable in a first mode of operation for startup during which an voltage is applied to the second node that increases towards a supply threshold. In response to the voltage at the second node reaching the supply threshold, the voltage regulator transitions to a second mode of operation where a programmable regulated voltage (higher than the supply threshold) is applied to the second node. In response to receipt of a low-power operation request, a first high-drive regulator circuitry is deactivated and a second low-power regulator circuitry is activated to provide a third mode of operation at low power.
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公开(公告)号：US11906995B2
公开(公告)日：2024-02-20
申请号：US17836417
申请日：2022-06-09
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Francesco Clerici , Pasquale Butta'
Abstract: A voltage regulator coupled between a first node and second node includes a first (full-power) regulator circuit and a second (low-power) regulator circuit. In a first mode: the first regulator circuit is activated (with the second regulator circuit inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is kept de-activated when the voltage at the first node is a ground voltage. In a second mode: the first regulator circuitry in is active (with the second regulator circuitry inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is inactive when the voltage at the first node is a ground voltage. In a third mode: the second regulator circuitry is active (with the first regulator circuitry inactive) irrespective of the voltage at the first node being at the battery voltage or the ground voltage.
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公开(公告)号：US20210357015A1
公开(公告)日：2021-11-18
申请号：US16874020
申请日：2020-05-14
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Michele Alessandro Carrano , Pasquale Butta' , Sergio Abenda
IPC: G06F1/3234 , H03K3/037
Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.
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公开(公告)号：US20200280332A1
公开(公告)日：2020-09-03
申请号：US16800793
申请日：2020-02-25
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Pasquale Butta'
Abstract: A method for power management in an electronic circuit that comprises a processing system and an RF embedded circuit includes: generating a first regulated voltage with a power regulation module of the RF embedded circuit; generating a second regulated voltage from the first regulated voltage with a first linear regulator of the processing system; and controlling the power regulation module of the RF embedded circuit to operate according to a plurality of operation modes. The operation modes include: a first sleep mode in which a switched-mode power supply of the RF embedded circuit is off and a second linear regulator of the RF embedded circuit is off; a second sleep mode in which a switched-mode power supply is off and the second linear regulator is on; and a third sleep mode in which the switched-mode power supply is on and the second linear regulator is off.
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