公开(公告)号：US20190114400A1

公开(公告)日：2019-04-18

申请号：US16150810

申请日：2018-10-03

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Stefano Lunghi ,  Albert Martinez

IPC: G06F21/12 ,  G06F21/14 ,  G06F12/14 ,  G06F21/60 ,  G06F21/72 ,  G06F21/74 ,  H04L9/06 ,  G06F9/445

Abstract: An electronic device includes: a non-volatile memory configured to store data including encrypted data; and a digital circuit. The digital circuit includes: a microprocessor configured to access the non-volatile memory and an internal memory; and a decryption circuit arranged on an interconnect network identifying an internal data path for exchanging the data between the non-volatile memory and the microprocessor, and connected to a memory controller of the non-volatile memory for receiving blocks of data from the non-volatile memory, the decryption circuit being configured to: perform a decryption on the fly of blocks of the data read from the non-volatile memory to obtain read decrypted data; generate first decryption masks corresponding to first blocks of data being read from the non-volatile memory at a given read address; and generate second decryption masks corresponding to second blocks of data to be read from the non-volatile memory at a next estimated read address.

公开(公告)号：US11023566B2

公开(公告)日：2021-06-01

申请号：US16150810

申请日：2018-10-03

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Stefano Lunghi ,  Albert Martinez

IPC: H04L29/00 ,  G06F21/12 ,  G06F12/14 ,  G06F21/72 ,  G06F21/79 ,  G06F9/445 ,  G06F21/14 ,  G06F21/60 ,  G06F21/74 ,  H04L9/06

Abstract: An electronic device includes: a non-volatile memory configured to store data including encrypted data; and a digital circuit. The digital circuit includes: a microprocessor configured to access the non-volatile memory and an internal memory; and a decryption circuit arranged on an interconnect network identifying an internal data path for exchanging the data between the non-volatile memory and the microprocessor, and connected to a memory controller of the non-volatile memory for receiving blocks of data from the non-volatile memory, the decryption circuit being configured to: perform a decryption on the fly of blocks of the data read from the non-volatile memory to obtain read decrypted data; generate first decryption masks corresponding to first blocks of data being read from the non-volatile memory at a given read address; and generate second decryption masks corresponding to second blocks of data to be read from the non-volatile memory at a next estimated read address.