公开(公告)号：US08570085B2

公开(公告)日：2013-10-29

申请号：US13689476

申请日：2012-11-29

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International NV

Inventor： Andrea Mario Veggetti ,  Abhishek Jain ,  Pankaj Rohilla

IPC: H03K3/289 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/0375 ,  H03K3/356008 ,  H03K19/0016

Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

Abstract translation: 本公开涉及一种具有数据保持功能的低功耗触发器电路，包括至少一个触发器和连接到触发器的输出的至少一个保持单元，并配置为使得在触发器的正常操作期间 电路中，保持单元将触发器的输出端子上存在的数据或逻辑状态发送到其自己的输出端子，而在触发器电路的低功耗操作期间，保持单元的锁存电路适合于存储数据或 激活与触发器的输出端子上存在的最后数据或逻辑状态对应的逻辑状态。

公开(公告)号：US20130088272A1

公开(公告)日：2013-04-11

申请号：US13689476

申请日：2012-11-29

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International NV

Inventor： Andrea Mario Veggetti ,  Abhishek Jain ,  Pankaj Rohilla

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K3/0375 ,  H03K3/356008 ,  H03K19/0016

Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

Abstract translation: 本公开涉及一种具有数据保持功能的低功耗触发器电路，包括至少一个触发器和连接到触发器的输出的至少一个保持单元，并配置为使得在触发器的正常操作期间 电路中，保持单元将触发器的输出端子上存在的数据或逻辑状态发送到其自己的输出端子，而在触发器电路的低功耗操作期间，保持单元的锁存电路适合于存储数据或 激活与触发器的输出端子上存在的最后数据或逻辑状态对应的逻辑状态。