公开(公告)号：US08570085B2

公开(公告)日：2013-10-29

申请号：US13689476

申请日：2012-11-29

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International NV

Inventor： Andrea Mario Veggetti ,  Abhishek Jain ,  Pankaj Rohilla

IPC: H03K3/289 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/0375 ,  H03K3/356008 ,  H03K19/0016

Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

Abstract translation: 本公开涉及一种具有数据保持功能的低功耗触发器电路，包括至少一个触发器和连接到触发器的输出的至少一个保持单元，并配置为使得在触发器的正常操作期间 电路中，保持单元将触发器的输出端子上存在的数据或逻辑状态发送到其自己的输出端子，而在触发器电路的低功耗操作期间，保持单元的锁存电路适合于存储数据或 激活与触发器的输出端子上存在的最后数据或逻辑状态对应的逻辑状态。

公开(公告)号：US20130088272A1

公开(公告)日：2013-04-11

申请号：US13689476

申请日：2012-11-29

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International NV

Inventor： Andrea Mario Veggetti ,  Abhishek Jain ,  Pankaj Rohilla

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K3/0375 ,  H03K3/356008 ,  H03K19/0016

Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

Abstract translation: 本公开涉及一种具有数据保持功能的低功耗触发器电路，包括至少一个触发器和连接到触发器的输出的至少一个保持单元，并配置为使得在触发器的正常操作期间 电路中，保持单元将触发器的输出端子上存在的数据或逻辑状态发送到其自己的输出端子，而在触发器电路的低功耗操作期间，保持单元的锁存电路适合于存储数据或 激活与触发器的输出端子上存在的最后数据或逻辑状态对应的逻辑状态。

公开(公告)号：US09543044B2

公开(公告)日：2017-01-10

申请号：US14074341

申请日：2013-11-07

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.R.L.

Inventor： Abhishek Jain ,  Andrea Mario Veggetti ,  Amit Chhabra

IPC: G11C29/48 ,  G06F1/08 ,  G11C29/24 ,  G11C29/52 ,  G11C29/54

CPC classification number: G11C29/48 ,  G06F1/08 ,  G06F11/00 ,  G11C29/24 ,  G11C29/52

Abstract: According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.

Abstract translation: 根据本文描述的实施例，用于测试存储器的方法包括在存储器处接收地址和起始信号，并且响应于起始信号在测试电路产生第一检测器脉冲。 第一检测器脉冲具有前沿和后沿。 检测与地址相关联的位的数据转换。 该位是一个功能位。 该方法还包括通过确定在后沿之后是否发生数据转换来确定该位是否为弱位。

公开(公告)号：US20200007129A1

公开(公告)日：2020-01-02

申请号：US16452051

申请日：2019-06-25

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Andrea Mario Veggetti ,  Abhishek Jain

IPC: H03K19/003 ,  H03K3/037 ,  H03K3/356 ,  G01R31/3181 ,  G11C7/10

Abstract: A latch is provided. The latch includes a plurality of storage nodes including a plurality of data storage nodes configured to store a data bit having one of two states and a plurality of complementary data storage nodes configured to store a complement of the data bit. The latch includes a plurality of supply voltage multi-dependency stages respectively corresponding to the plurality of storage nodes. Each supply voltage multi-dependency stage has an output coupled to a storage node and at least two control inputs respectively coupled to at least two other storage nodes of the plurality of storage nodes. The supply voltage multi-dependency stage is configured to cause a state of the data bit stored in the storage node to change from a first state to a second state in response a change in both states of two data bits respectively stored in the at least two other storage nodes.