Harvard architecture microprocessor having a linear addressable space
    1.
    发明申请
    Harvard architecture microprocessor having a linear addressable space 有权
    哈佛架构微处理器具有线性可寻址空间

    公开(公告)号:US20040073762A1

    公开(公告)日:2004-04-15

    申请号:US10645321

    申请日:2003-08-21

    CPC classification number: G06F13/4022

    Abstract: A microprocessor is connected to a first memory space through a first bus and to a second memory space through a second bus. The microprocessor includes a processing unit that includes a program bus and a data bus, and an interface unit connected, on one side, to the program bus and to the data bus and, on the other side, to the first and second buses. The interface includes a switching circuit for connecting the program bus and the data bus, respectively, to either the first bus or the second bus, in accordance with respective requests for accessing the program and data sent by the processing unit.

    Abstract translation: 微处理器通过第一总线连接到第一存储器空间,并通过第二总线连接到第二存储器空间。 微处理器包括一个处理单元,它包括一个程序总线和一个数据总线,一个接口单元一方面连接到程序总线和数据总线,另一侧连接到第一和第二总线。 接口包括根据访问程序和由处理单元发送的数据的相应请求,将程序总线和数据总线分别连接到第一总线或第二总线的切换电路。

    Microprocessor having an extended addressable space
    2.
    发明申请
    Microprocessor having an extended addressable space 有权
    微处理器具有扩展的可寻址空间

    公开(公告)号:US20040243786A1

    公开(公告)日:2004-12-02

    申请号:US10814823

    申请日:2004-03-31

    CPC classification number: G06F9/342

    Abstract: A microprocessor includes a processing unit, an address bus connected to an addressable memory space, and executes instructions from an instruction set for accessing the addressable memory space. The addressable memory space is for a lower memory area and an extended memory area. The instruction set includes a first instruction group for accessing the lower memory area, and a second instruction group that is distinct from the first instruction group for accessing the extended memory area.

    Abstract translation: 微处理器包括处理单元,连接到可寻址存储器空间的地址总线,并且执行来自用于访问可寻址存储器空间的指令集的指令。 可寻址存储器空间用于较低的存储区域和扩展存储区域。 指令集包括用于访问下部存储器区域的第一指令组和与用于访问扩展存储器区域的第一指令组不同的第二指令组。

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