公开(公告)号：US20040017722A1

公开(公告)日：2004-01-29

申请号：US10438733

申请日：2003-05-15

Applicant: STMicroelectronics SA

Inventor： Paola Cavaleri ,  Bruno Leconte ,  Sebastien Zink ,  Jean Devin

IPC: G11C007/00

CPC classification number: G11C16/3431 ,  G11C16/16 ,  G11C16/3418

Abstract: The present invention relates to a page-erasable FLASH memory including a memory array having a plurality of pages each with floating-gate transistors connected by their gates to word lines, a word line decoder connected to the word lines of the memory, and the application of a positive erase voltage to the source or drain electrodes of all the floating-gate transistors of a sector forming a page to be erased. According to the present invention, the word line decoder includes a unit for applying, when a page is being erased, a negative erase voltage to the gates of the transistors of the page to be erased, while applying a positive inhibit voltage to the gates of the transistors of at least one page that is not to be erased.