公开(公告)号：US11190236B2

公开(公告)日：2021-11-30

申请号：US17080431

申请日：2020-10-26

Applicant: STMicroelectronics SA

Inventor： Marc Houdebine ,  Laurent Jean Garcia

IPC: H04B5/00 ,  H04W56/00 ,  H04L7/033

Abstract: An embodiment near-field communication device using active load modulation, in card emulation mode and intended to communicate with a reader, comprises a digital phase-locked loop configured to generate a carrier signal, having an oscillator configured to generate the carrier signal in a manner controlled by an analog control signal, a feedback circuit configured to generate a digital control signal, a digital-to-analog converter configured to convert the digital control signal into the analog control signal, and an integrator assembly configured to integrate the analog control signal.

公开(公告)号：US20210126672A1

公开(公告)日：2021-04-29

申请号：US17080431

申请日：2020-10-26

Applicant: STMicroelectronics SA

Inventor： Marc Houdebine ,  Laurent Jean Garcia

IPC: H04B5/00 ,  H04L7/033

Abstract: An embodiment near-field communication device using active load modulation, in card emulation mode and intended to communicate with a reader, comprises a digital phase-locked loop configured to generate a carrier signal, having an oscillator configured to generate the carrier signal in a manner controlled by an analog control signal, a feedback circuit configured to generate a digital control signal, a digital-to-analog converter configured to convert the digital control signal into the analog control signal, and an integrator assembly configured to integrate the analog control signal.

公开(公告)号：US20240014809A1

公开(公告)日：2024-01-11

申请号：US18345726

申请日：2023-06-30

Applicant: STMicroelectronics SA

Inventor： Laurent Jean Garcia ,  Marc Houdebine

IPC: H03K3/03 ,  H03K5/1252

CPC classification number: H03K3/0315 ,  H03K5/1252

Abstract: A clock generator circuit includes an oscillator circuit coupled to a bias circuit. The bias circuit includes a current mirror, third and fourth transistors, and a cascode transistor. The current mirror includes a reference transistor and a set of copy transistors that are programmable. The third transistor has a source connected to a cold spot, a drain and a gate connected to this drain. The fourth transistor has a source connected to the drain of the third transistor, a drain, and a gate connected to that drain. The cascode transistor has a source connected to a drain of at least one of the copy transistors, a drain, and a gate connected to the gate of the fourth transistor. The gates of the fourth transistor and the cascode transistor are thicker than the gates of the reference transistor, each copy transistor, and the third transistor.