公开(公告)号：US20030216088A1

公开(公告)日：2003-11-20

申请号：US10436881

申请日：2003-05-13

Applicant: STMicroelectronics SA

Inventor： Olivier Tardieu ,  Christophe Moreaux ,  Ahmed Kari

IPC: H01R009/22

CPC classification number: H03K19/09429

Abstract: A buffer of reduced size includes a logic gate to raise the potential level of input digital data having a first logic level to a potential equal to a low power supply potential, and to produce intermediate data if a validation signal is active. The buffer also includes a tristate inverter to produce output data, at an output, that are logically inverse to the intermediate data if the validation signal is active and having its output at high impedance if otherwise. Such a buffer is particularly useful as an output buffer for contact cards using a power supply potential different from a potential powering a reader with which the card communicates.

Abstract translation: 减小尺寸的缓冲器包括逻辑门，以将具有第一逻辑电平的输入数字数据的电位电平提高到等于低电源电位的电位，并且如果有效信号是有效的，则产生中间数据。 缓冲器还包括一个三态反相器，用于在输出端产生与中间数据逻辑相反的输出数据，如果验证信号是有效的，并且如果有的话，其输出为高阻抗。 这样的缓冲器特别适用于使用电源电位不同于为卡通信的读取器供电的接触卡的输出缓冲器。