公开(公告)号：US20030216088A1

公开(公告)日：2003-11-20

申请号：US10436881

申请日：2003-05-13

Applicant: STMicroelectronics SA

Inventor： Olivier Tardieu ,  Christophe Moreaux ,  Ahmed Kari

IPC: H01R009/22

CPC classification number: H03K19/09429

Abstract: A buffer of reduced size includes a logic gate to raise the potential level of input digital data having a first logic level to a potential equal to a low power supply potential, and to produce intermediate data if a validation signal is active. The buffer also includes a tristate inverter to produce output data, at an output, that are logically inverse to the intermediate data if the validation signal is active and having its output at high impedance if otherwise. Such a buffer is particularly useful as an output buffer for contact cards using a power supply potential different from a potential powering a reader with which the card communicates.

Abstract translation: 减小尺寸的缓冲器包括逻辑门，以将具有第一逻辑电平的输入数字数据的电位电平提高到等于低电源电位的电位，并且如果有效信号是有效的，则产生中间数据。 缓冲器还包括一个三态反相器，用于在输出端产生与中间数据逻辑相反的输出数据，如果验证信号是有效的，并且如果有的话，其输出为高阻抗。 这样的缓冲器特别适用于使用电源电位不同于为卡通信的读取器供电的接触卡的输出缓冲器。

公开(公告)号：US20040010728A1

公开(公告)日：2004-01-15

申请号：US10438289

申请日：2003-05-13

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics SA

Inventor： Orazio Musumeci ,  Ahmed Kari

IPC: G06F001/12

CPC classification number: H03K5/19 ,  H03K5/1252 ,  H04L7/044

Abstract: A start-detection circuit and a stop-detection circuit detect the start condition and the stop condition in a data signal associated with a clock signal according to the IIC protocol. The start-detection circuit comprises: a first detector to produce a first reset signal when a trailing edge of the data signal is detected; a counter to count pulses of a reference signal when the first reset signal is received, and to produce an enabling signal when the number of pulses counted has reached a predefined number; a second detector to store the enabling signal when a trailing edge of the clock signal is detected. The stop-detection circuit comprises a third detector to produce a stop signal when a leading edge of the data signal is detected after the detection of a leading edge of the clock signal.

Abstract translation: 启动检测电路和停止检测电路根据IIC协议检测与时钟信号相关联的数据信号中的启动条件和停止条件。 启动检测电路包括：当检测到数据信号的后沿时产生第一复位信号的第一检测器; 计数器，当接收到第一复位信号时计数参考信号的脉冲，并且当计数的脉冲数达到预定数量时产生使能信号; 当检测到时钟信号的后沿时，存储启用信号的第二检测器。 停止检测电路包括第三检测器，当在检测到时钟信号的前沿之后检测到数据信号的前沿时产生停止信号。