公开(公告)号：US20200184110A1

公开(公告)日：2020-06-11

申请号：US16213500

申请日：2018-12-07

Applicant: STMicroelectronics SA ,  INSTITUT POLYTECHNIQUE DE GRENOBLE

Inventor： Sophie Germain ,  Sylvain Engels ,  Laurent Fesquet

IPC: G06F21/72 ,  G06F21/75 ,  G06F21/60 ,  G06F21/77 ,  H03K5/14

Abstract: An asynchronous pipeline circuit includes: a first processing stage including a first data latch configured to generate a request signal; a second processing stage downstream the first processing stage and including a second data latch; and a programmable delay line coupled between the first data latch and the second processing stage. The programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal on each data transfer from the first data latch to the second data latch.

公开(公告)号：US11151287B2

公开(公告)日：2021-10-19

申请号：US16213500

申请日：2018-12-07

Applicant: STMicroelectronics SA ,  INSTITUT POLYTECHNIQUE DE GRENOBLE

Inventor： Sophie Germain ,  Sylvain Engels ,  Laurent Fesquet

IPC: G06F21/00 ,  G06F21/72 ,  G06F21/75 ,  G06F21/60 ,  H03K5/14 ,  G06F21/77 ,  H03K5/00 ,  H03K19/20

Abstract: An asynchronous pipeline circuit includes: a first processing stage including a first data latch configured to generate a request signal; a second processing stage downstream the first processing stage and including a second data latch; and a programmable delay line coupled between the first data latch and the second processing stage. The programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal on each data transfer from the first data latch to the second data latch.