公开(公告)号：US20200184110A1

公开(公告)日：2020-06-11

申请号：US16213500

申请日：2018-12-07

Applicant: STMicroelectronics SA ,  INSTITUT POLYTECHNIQUE DE GRENOBLE

Inventor： Sophie Germain ,  Sylvain Engels ,  Laurent Fesquet

IPC: G06F21/72 ,  G06F21/75 ,  G06F21/60 ,  G06F21/77 ,  H03K5/14

Abstract: An asynchronous pipeline circuit includes: a first processing stage including a first data latch configured to generate a request signal; a second processing stage downstream the first processing stage and including a second data latch; and a programmable delay line coupled between the first data latch and the second processing stage. The programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal on each data transfer from the first data latch to the second data latch.

公开(公告)号：US11151287B2

公开(公告)日：2021-10-19

申请号：US16213500

申请日：2018-12-07

Applicant: STMicroelectronics SA ,  INSTITUT POLYTECHNIQUE DE GRENOBLE

Inventor： Sophie Germain ,  Sylvain Engels ,  Laurent Fesquet

IPC: G06F21/00 ,  G06F21/72 ,  G06F21/75 ,  G06F21/60 ,  H03K5/14 ,  G06F21/77 ,  H03K5/00 ,  H03K19/20

Abstract: An asynchronous pipeline circuit includes: a first processing stage including a first data latch configured to generate a request signal; a second processing stage downstream the first processing stage and including a second data latch; and a programmable delay line coupled between the first data latch and the second processing stage. The programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal on each data transfer from the first data latch to the second data latch.

公开(公告)号：US11616516B2

公开(公告)日：2023-03-28

申请号：US17664987

申请日：2022-05-25

Applicant: STMICROELECTRONICS SA

Inventor： Pierre Dautriche ,  Sylvain Engels

IPC: H04B1/00 ,  H04B1/04 ,  G06N3/02

Abstract: According to one aspect, an embodiment radio frequency receiver device comprises an input interface configured to receive a radio frequency signal of a given type and convert same into an electric signal, a detector configured to detect at least one voltage level in the electric signal, a pulse generator configured to generate at least one pulse train representative of the voltage levels detected, and a processing unit configured to determine the type of the radio frequency signal from the at least one pulse train.

公开(公告)号：US20140089885A1

公开(公告)日：2014-03-27

申请号：US14028188

申请日：2013-09-16

Applicant: STMicroelectronics SA

Inventor： Julien Le Coz ,  Sylvain Engels ,  Alain Tournier

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/505 ,  G06F2217/84

Abstract: A first assembly of critical cells is to be monitored. An equivalent capacitance of output cells coupled to the critical path is determined. Logic level inputs of the critical cells for signal propagation are also determined. A second assembly of control logic cells is provided which copies the first assembly in terms of number of cells, type of cells and cell connection such that each of the control cells is a homolog of a corresponding critical cell. Charge cells are provided at the outputs of the control cells having an equivalent capacitance in accordance with the determined capacitance of the output cells. For each control cell, logic levels are asserted in accordance with the determined configuration of the critical path. A signal generator applies a signal the input of the second assembly and a signal receiver is coupled to the output of the second assembly.

Abstract translation: 要监测关键电池的第一组装。 确定耦合到关键路径的输出单元的等效电容。 信号传播的关键单元的逻辑电平输入也被确定。 提供了控制逻辑单元的第二组件，其根据单元的数量，单元的类型和单元连接复制第一组件，使得每个控制单元是相应的关键单元的同源物。 根据所确定的输出单元的电容，在具有等效电容的控制单元的输出处提供充电单元。 对于每个控制单元，根据确定的关键路径的配置来确定逻辑电平。 信号发生器将信号施加到第二组件的输入端，信号接收器耦合到第二组件的输出。

公开(公告)号：US20210399749A1

公开(公告)日：2021-12-23

申请号：US17328612

申请日：2021-05-24

Applicant: STMicroelectronics SA

Inventor： Pierre Dautriche ,  Sylvain Engels

IPC: H04B1/00 ,  H04B1/04 ,  G06N3/02

Abstract: According to one aspect, an embodiment radio frequency receiver device comprises an input interface configured to receive a radio frequency signal of a given type and convert same into an electric signal, a detector configured to detect at least one voltage level in the electric signal, a pulse generator configured to generate at least one pulse train representative of the voltage levels detected, and a processing unit configured to determine the type of the radio frequency signal from the at least one pulse train.

公开(公告)号：US10804885B2

公开(公告)日：2020-10-13

申请号：US16654261

申请日：2019-10-16

Applicant: STMicroelectronics SA

Inventor： Sylvain Engels ,  Alain Aurand ,  Etienne Maurin

IPC: H03K3/00 ,  H03K3/356 ,  H01L27/02 ,  H03K3/3562 ,  H03K19/0948 ,  H01L23/528

Abstract: A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).

公开(公告)号：US20220286149A1

公开(公告)日：2022-09-08

申请号：US17664987

申请日：2022-05-25

Applicant: STMICROELECTRONICS SA

Inventor： Pierre Dautriche ,  Sylvain Engels

IPC: H04B1/00 ,  G06N3/02 ,  H04B1/04

Abstract: According to one aspect, an embodiment radio frequency receiver device comprises an input interface configured to receive a radio frequency signal of a given type and convert same into an electric signal, a detector configured to detect at least one voltage level in the electric signal, a pulse generator configured to generate at least one pulse train representative of the voltage levels detected, and a processing unit configured to determine the type of the radio frequency signal from the at least one pulse train.

公开(公告)号：US11374597B2

公开(公告)日：2022-06-28

申请号：US17328612

申请日：2021-05-24

Applicant: STMicroelectronics SA

Inventor： Pierre Dautriche ,  Sylvain Engels

IPC: H04B1/00 ,  H04B1/04 ,  G06N3/02

Abstract: According to one aspect, an embodiment radio frequency receiver device comprises an input interface configured to receive a radio frequency signal of a given type and convert same into an electric signal, a detector configured to detect at least one voltage level in the electric signal, a pulse generator configured to generate at least one pulse train representative of the voltage levels detected, and a processing unit configured to determine the type of the radio frequency signal from the at least one pulse train.

公开(公告)号：US09746863B2

公开(公告)日：2017-08-29

申请号：US14960052

申请日：2015-12-04

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou ,  Julien Le Coz ,  Sylvain Engels

IPC: H01L23/34 ,  G05F1/46 ,  H01L27/02 ,  H01L27/06

CPC classification number: G05F1/463 ,  H01L23/345 ,  H01L27/0251 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device includes an integrated circuit with a MOS transistor and a heating circuit electrically coupled to at least two points of one of the source or drain semiconductive region of the transistor. A portion of the source or drain semiconductive region between the two points forms a resistive element. The heating circuit is configured to cause a current to circulate through the resistive element between the two points to heat an active region of the transistor.

公开(公告)号：US20160370815A1

公开(公告)日：2016-12-22

申请号：US14960052

申请日：2015-12-04

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou ,  Julien Le Coz ,  Sylvain Engels

IPC: G05F1/46

CPC classification number: G05F1/463 ,  H01L23/345 ,  H01L27/0251 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device includes an integrated circuit with a MOS transistor and a heating circuit electrically coupled to at least two points of one of the source or drain semiconductive region of the transistor. A portion of the source or drain semiconductive region between the two points forms a resistive element. The heating circuit is configured to cause a current to circulate through the resistive element between the two points to heat an active region of the transistor.

Abstract translation: 电子器件包括具有MOS晶体管的集成电路和与该晶体管的源极或半导体半导体区域中的至少两个点的至少两个点电耦合的加热电路。 两点之间的源极或漏极半导体区域的一部分形成电阻元件。 加热电路被配置为使电流在两个点之间循环通过电阻元件，以加热晶体管的有源区。