MEMORY INTERFACE WITH CONFIGURABLE HIGH-SPEED SERIAL DATA LANES FOR HIGH BANDWIDTH MEMORY

    公开(公告)号:US20220254390A1

    公开(公告)日:2022-08-11

    申请号:US17666255

    申请日:2022-02-07

    发明人: Dean Gans Aran Ziv

    IPC分类号: G11C7/10 H03K19/20

    摘要: A memory module including a memory array of storage transistors and a control circuit where the control circuit includes a memory interface for providing high bandwidth access to the memory array on serial data lanes. In some embodiments, the control circuit of a memory module includes multiple transceivers for connecting to serial data lanes. In one embodiment, the memory interface of a memory module configures some transceivers for host connection or for upstream connection to an upstream memory module and configures other transceivers for downstream connection to a downstream memory module. In other embodiments, a multi-module memory device is formed using multiple memory modules connected in a cascade configuration or in a star configuration to provide high bandwidth memory access to all memory locations of the multiple memory modules using the given number of serial data lanes of the host connection.

    Memory interface with configurable high-speed serial data lanes for high bandwidth memory

    公开(公告)号:US11810640B2

    公开(公告)日:2023-11-07

    申请号:US17666255

    申请日:2022-02-07

    发明人: Dean Gans Aran Ziv

    IPC分类号: G11C7/10 H03K19/20

    摘要: A memory module including a memory array of storage transistors and a control circuit where the control circuit includes a memory interface for providing high bandwidth access to the memory array on serial data lanes. In some embodiments, the control circuit of a memory module includes multiple transceivers for connecting to serial data lanes. In one embodiment, the memory interface of a memory module configures some transceivers for host connection or for upstream connection to an upstream memory module and configures other transceivers for downstream connection to a downstream memory module. In other embodiments, a multi-module memory device is formed using multiple memory modules connected in a cascade configuration or in a star configuration to provide high bandwidth memory access to all memory locations of the multiple memory modules using the given number of serial data lanes of the host connection.