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公开(公告)号：US10698754B2
公开(公告)日：2020-06-30
申请号：US16104788
申请日：2018-08-17
申请人： Syntiant
摘要： A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii) second values stored in a digital non-volatile memory; performing, by the circuitry, operations comprising a comparison of the first values and the second values; analyzing, by the circuitry, results of the comparison to determine whether an error is greater than or equal to a predefined threshold; responsive to determining the error is greater than or equal to the predefined threshold, initiating, by the circuitry, operations to reprogram the analog array with the second value is described.
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公开(公告)号：US20190050721A1
公开(公告)日：2019-02-14
申请号：US16101280
申请日：2018-08-10
申请人： Syntiant
摘要： Disclosed herein is a neuromorphic integrated circuit, including in many embodiments, a neural network disposed in a multiplier array in a memory sector of the integrated circuit, and a plurality of multipliers of the multiplier array, a multiplier thereof including at least one transistor-based cell configured to store a synaptic weight of the neural network, an input configured to accept digital input pulses for the multiplier, an output configured to provide digital output pulses of the multiplier, and a charge integrator, where the charge integrator is configured to integrate a current associated with an input pulse of the input pulses over an input pulse width thereof, and where the multiplier is configured to provide an output pulse of the output pulses with an output pulse width proportional to the input pulse width.
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公开(公告)号：US20220414439A1
公开(公告)日：2022-12-29
申请号：US17892876
申请日：2022-08-22
申请人： SYNTIANT
摘要： Disclosed herein is a method for automatically generating an integrated circuit. The method includes receiving a behavioral description of at least the first layer of the neural network, converting the behavioral description of the first layer of the neural network into the computational graph, converting a computational graph to a circuit netlist based on a correlation of: (i) operations described in the computational graph, and (ii) an analog cell library including a plurality of predetermined circuit blocks that describe known neural network operations, generating a circuit layout that corresponds to at least a first layer of a neural network, and performing additional actions configured to cause generation of the integrated circuit based on the circuit layout. In some situations, the behavioral description defines an architecture of machine learning logic that represents at least a portion of the neural network. Additionally, in some situations, each cell of the integrated circuit includes a metal-oxide-semiconductor field-effect transistor (“MOSFET”).
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公开(公告)号：US11423288B2
公开(公告)日：2022-08-23
申请号：US16039142
申请日：2018-07-18
申请人： Syntiant
摘要： Disclosed herein is a method for automatically generating an integrated circuit. The method includes receiving a behavioral description of at least the first layer of the neural network, converting the behavioral description of the first layer of the neural network into the computational graph, converting a computational graph to a circuit netlist based on a correlation of: (i) operations described in the computational graph, and (ii) an analog cell library including a plurality of predetermined circuit blocks that describe known neural network operations, generating a circuit layout that corresponds to at least a first layer of a neural network, and performing additional actions configured to cause generation of the integrated circuit based on the circuit layout. In some situations, the behavioral description defines an architecture of machine learning logic that represents at least a portion of the neural network. Additionally, in some situations, each cell of the integrated circuit includes a metal-oxide-semiconductor field-effect transistor (“MOSFET”).
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公开(公告)号：US20220188619A1
公开(公告)日：2022-06-16
申请号：US17683125
申请日：2022-02-28
申请人： SYNTIANT
摘要： Disclosed is a neuromorphic-processing systems including, in some embodiments, a special-purpose host processor operable as a stand-alone host processor; a neuromorphic co-processor including an artificial neural network; and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The co-processor is configured to enhance special-purpose processing of the host processor with the artificial neural network. Also disclosed is a method of a neuromorphic-processing system having the special-purpose host processor and the neuromorphic co-processor including, in some embodiments, enhancing the special-purpose processing of the host processor with the artificial neural network of the co-processor. In some embodiments, the host processor is a hearing-aid processor.
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公开(公告)号：US20220147807A1
公开(公告)日：2022-05-12
申请号：US17581453
申请日：2022-01-21
申请人： SYNTIANT
IPC分类号： G06N3/063 , G06N3/08 , H03K19/0944
摘要： Disclosed is a neuromorphic integrated circuit including, in some embodiments, a multi-layered neural network disposed in an analog multiplier array of two-quadrant multipliers. Each multiplier of the multipliers is wired to ground and draws a negligible amount of current when input signal values for input signals to transistors of the multiplier are approximately zero, weight values of the transistors of the multiplier are approximately zero, or a combination thereof. Also disclosed is a method of the neuromorphic integrated circuit including, in some embodiments, training the neural network; tracking rates of change for the weight values; determining if and how quickly certain weight values are trending toward zero; and driving those weight values toward zero, thereby encouraging sparsity in the neural network. Sparsity in the neural network combined with the multipliers wired to ground minimizes power consumption of the neuromorphic integrated circuit such that battery power is sufficient for power.
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公开(公告)号：US10949281B2
公开(公告)日：2021-03-16
申请号：US16892035
申请日：2020-06-03
申请人： SYNTIANT
摘要： A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii) second values stored in a digital non-volatile memory; performing, by the circuitry, operations comprising a comparison of the first values and the second values; analyzing, by the circuitry, results of the comparison to determine whether an error is greater than or equal to a predefined threshold; responsive to determining the error is greater than or equal to the predefined threshold, initiating, by the circuitry, operations to reprogram the analog array with the second value is described.
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公开(公告)号：US20190042931A1
公开(公告)日：2019-02-07
申请号：US16041565
申请日：2018-07-20
申请人： Syntiant
摘要： Disclosed is a neuromorphic integrated circuit including, in some embodiments, a multi-layered neural network disposed in an analog multiplier array of two-quadrant multipliers. Each multiplier of the multipliers is wired to ground and draws a negligible amount of current when input signal values for input signals to transistors of the multiplier are approximately zero, weight values of the transistors of the multiplier are approximately zero, or a combination thereof. Also disclosed is a method of the neuromorphic integrated circuit including, in some embodiments, training the neural network; tracking rates of change for the weight values; determining if and how quickly certain weight values are trending toward zero; and driving those weight values toward zero, thereby encouraging sparsity in the neural network. Sparsity in the neural network combined with the multipliers wired to ground minimizes power consumption of the neuromorphic integrated circuit such that battery power is sufficient for power.
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公开(公告)号：US20220237068A1
公开(公告)日：2022-07-28
申请号：US17717059
申请日：2022-04-09
申请人： SYNTIANT
摘要： A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii) second values stored in a digital non-volatile memory; performing, by the circuitry, operations comprising a comparison of the first values and the second values; analyzing, by the circuitry, results of the comparison to determine whether an error is greater than or equal to a predefined threshold; responsive to determining the error is greater than or equal to the predefined threshold, initiating, by the circuitry, operations to reprogram the analog array with the second value is described.
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公开(公告)号：US11334412B2
公开(公告)日：2022-05-17
申请号：US17201654
申请日：2021-03-15
申请人： SYNTIANT
摘要： A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii) second values stored in a digital non-volatile memory; performing, by the circuitry, operations comprising a comparison of the first values and the second values; analyzing, by the circuitry, results of the comparison to determine whether an error is greater than or equal to a predefined threshold; responsive to determining the error is greater than or equal to the predefined threshold, initiating, by the circuitry, operations to reprogram the analog array with the second value is described.
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