公开(公告)号：US20100146469A1

公开(公告)日：2010-06-10

申请号：US12332013

申请日：2008-12-10

Applicant: Salim U. Chowdhury

Inventor： Salim U. Chowdhury

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/84

Abstract: For each of a plurality of interconnected gates forming one or more non-critical timing paths through a logic block, a gate size may be selected based on (i) a gate delay, (ii) a change in gate delay and gate power associated with downsizing the gate to a next available gate size, and (iii) signal arrival times at one or more inputs and outputs of the gate to minimize power consumed by the logic block while maintaining a specified cycle time.

Abstract translation: 对于通过逻辑块形成一个或多个非关键定时路径的多个互连门中的每一个，栅极尺寸可以基于（i）栅极延迟，（ii）栅极延迟的变化和与 将门小型化为下一个可用的门尺寸，以及（iii）门的一个或多个输入和输出处的信号到达时间，以最小化由逻辑块消耗的功率，同时保持指定的周期时间。

公开(公告)号：US08612917B2

公开(公告)日：2013-12-17

申请号：US12437174

申请日：2009-05-07

Applicant: Salim U. Chowdhury

Inventor： Salim U. Chowdhury

IPC: G06F17/50 ,  G06F9/455 ,  G06F11/22

CPC classification number: G06F17/5031 ,  G06F2217/84

Abstract: A method for selecting gate sizes for a logic network of an integrated circuit, wherein the logic network is defined by a plurality of logic paths that includes nodes, gates and interconnect, includes assigning, at one or more computers, gate sizes to gates adjacent to timing path end nodes of the logic network, determining an n-tuple of performance/loading parameters for each of the assigned gate sizes based on gate and interconnect delay models, and determining whether two or more logic paths share a descendent gate. Two or more logic paths that share a descendent gate are coupled. The method also includes grouping the n-tuples of parameters of coupled logic paths into bins based on gate sizes of the shared descendent gate, recursively propagating, node by node, the bins of n-tuples of parameters along the coupled logic paths, detecting whether any of the bins of n-tuples of parameters are suboptimal for all of the coupled logic paths based on a comparison of the n-tuples of parameters in bin-pairs, and eliminating all n-tuples of parameters of the suboptimal bins along the coupled logic paths to prune gate sizes associated with the suboptimal bins.

Abstract translation: 一种用于选择集成电路的逻辑网络的栅极尺寸的方法，其中所述逻辑网络由包括节点，栅极和互连件的多个逻辑路径定义，包括在一个或多个计算机处将栅极尺寸分配给与其相邻的栅极 逻辑网络的定时路径端节点，基于门和互连延迟模型确定每个分配的门尺寸的性能/负载参数的n元组，​​以及确定两个或多个逻辑路径是否共享后代门。 共享后代门的两个或多个逻辑路径被耦合。 该方法还包括基于共享后代门的栅极大小，逐个递归地传播耦合的逻辑路径的n个元组，将沿着耦合逻辑路径的n元组的元组分组，检测是否 基于对二进制对参数的n元组的比较，并且消除所有耦合的逻辑路径中n个元组的任何一个n个元组，沿着耦合的 修剪与次佳箱相关的门尺寸的逻辑路径。

公开(公告)号：US08176459B2

公开(公告)日：2012-05-08

申请号：US12332013

申请日：2008-12-10

Applicant: Salim U. Chowdhury

Inventor： Salim U. Chowdhury

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/84

Abstract: For each of a plurality of interconnected gates forming one or more non-critical timing paths through a logic block, a gate size may be selected based on (i) a gate delay, (ii) a change in gate delay and gate power associated with downsizing the gate to a next available gate size, and (iii) signal arrival times at one or more inputs and outputs of the gate to minimize power consumed by the logic block while maintaining a specified cycle time.

Abstract translation: 对于通过逻辑块形成一个或多个非关键定时路径的多个互连门中的每一个，栅极尺寸可以基于（i）栅极延迟，（ii）栅极延迟的变化和与 将门小型化为下一个可用的门尺寸，以及（iii）门的一个或多个输入和输出处的信号到达时间，以最小化由逻辑块消耗的功率，同时保持指定的周期时间。

公开(公告)号：US07454730B1

公开(公告)日：2008-11-18

申请号：US11293058

申请日：2005-12-02

Applicant: Salim U. Chowdhury

Inventor： Salim U. Chowdhury

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A method for inserting repeaters into an integrated circuit synthesis is provided. The method initiates with identifying possible repeater insertion locations along a signal routing pathway within an integrated circuit design. The possible repeater insertion locations are organized in a tree enabling bottom-up traversal. A set of solutions for each of the insertion locations is generated while traversing the tree in a first direction and the set of solutions is organized in a first and a second set, the first set ordered by a late mode capacitive load and the second set order by an early mode capacitive load. A computer readable medium including program instructions representing the method operations and a system are also included.

Abstract translation: 提供了一种将中继器插入到集成电路合成中的方法。 该方法通过在集成电路设计中沿着信号路由路径识别可能的中继器插入位置来启动。 可能的中继器插入位置被组织在树中，从而能够进行自下而上遍历。 每个插入位置的一组解决方案在沿第一方向遍历树时产生，并且该组解被组织在第一和第二组中，第一组由晚期模式电容性负载排序，而第二组顺序 通过早期模式容性负载。 还包括包括表示方法操作的程序指令和系统的计算机可读介质。

公开(公告)号：US09317641B2

公开(公告)日：2016-04-19

申请号：US12880275

申请日：2010-09-13

Applicant: Salim U. Chowdhury ,  Georgios Konstadinidis

Inventor： Salim U. Chowdhury ,  Georgios Konstadinidis

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/78 ,  G06F2217/84

Abstract: A processing device can identify gates of an integrated circuit design having a slack value less than a predefined slack threshold. The processing device can further, for each of the identified gates, determine (i) a number of nodes of the integrated circuit design that experience a timing slack improvement if the gate is swapped with an alternative implementation having a reduced delay or (ii) a sum of timing slack improvements experienced by nodes of the integrated circuit design if the gate is swapped with the alternative implementation having a reduced delay. The processing device can still further swap the gate with the alternative implementation having the reduced delay if the determined number or sum is greater than a corresponding predetermined threshold.

Abstract translation: 处理装置可以识别具有小于预定义的松弛阈值的松弛值的集成电路设计的门。 对于每个所识别的门，处理装置还可以进一步确定（i）集成电路设计的节点数量，如果用具有减小的延迟的替代实施方式交换门，则可以经历定时松弛改善，或者（ii） 如果与具有减小的延迟的替代实施方式交换门，集成电路设计的节点经历的定时松弛改进的总和。 如果所确定的数量或或大于相应的预定阈值，则处理装置还可以用具有减小的延迟的替代实施方式进一步交换门。

公开(公告)号：US20120066658A1

公开(公告)日：2012-03-15

申请号：US12880275

申请日：2010-09-13

Applicant: Salim U. Chowdhury ,  Georgios Konstadinidis

Inventor： Salim U. Chowdhury ,  Georgios Konstadinidis

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/78 ,  G06F2217/84

Abstract: A system for selecting gates for an integrated circuit design may include at least one processing device configured to identify gates of the integrated circuit design having a slack value less than a predefined slack threshold. The at least one processing device may be further configured to, for each of the identified gates, determine (i) a number of nodes of the integrated circuit design that experience a timing slack improvement if the gate is swapped with an alternative implementation having a reduced delay or (ii) a sum of timing slack improvements experienced by nodes of the integrated circuit design if the gate is swapped with the alternative implementation having a reduced delay. The at least one processing device may still be further configured to swap the gate with the alternative implementation having the reduced delay if the determined number or sum is greater than a corresponding predetermined threshold.

Abstract translation: 用于选择用于集成电路设计的门的系统可以包括至少一个处理装置，其被配置为识别具有小于预定义的松弛阈值的松弛值的集成电路设计的门。 所述至少一个处理设备还可以被配置为：对于每个所识别的门，确定（i）如果所述门与具有减少的替代实施方式交换，则所述集成电路设计的节点数量经历了定时松弛改善 延迟或（ii）如果与具有减小的延迟的替代实施方式交换门，则集成电路设计的节点经历的定时松弛改善的总和。 如果所确定的数量或或大于相应的预定阈值，则所述至少一个处理装置可以被进一步配置成与具有减小的延迟的替代实施方式交换所述门。

公开(公告)号：US20100287516A1

公开(公告)日：2010-11-11

申请号：US12437174

申请日：2009-05-07

Applicant: Salim U. Chowdhury

Inventor： Salim U. Chowdhury

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F2217/84

Abstract: A method for selecting gate sizes for a logic network of an integrated circuit, wherein the logic network is defined by a plurality of logic paths that includes nodes, gates and interconnect, includes assigning, at one or more computers, gate sizes to gates adjacent to timing path end nodes of the logic network, determining an n-tuple of performance/loading parameters for each of the assigned gate sizes based on gate and interconnect delay models, and determining whether two or more logic paths share a descendant gate. Two or more logic paths that share a descendent gate are coupled. The method also includes grouping the n-tuples of parameters of coupled logic paths into bins based on gate sizes of the shared descendent gate, recursively propagating, node by node, the bins of n-tuples of parameters along the coupled logic paths, detecting whether any of the bins of n-tuples of parameters are suboptimal for all of the coupled logic paths based on a comparison of the n-tuples of parameters in bin-pairs, and eliminating all n-tuples of parameters of the suboptimal bins along the coupled logic paths to prune gate sizes associated with the suboptimal bins.

Abstract translation: 一种用于选择集成电路的逻辑网络的栅极尺寸的方法，其中所述逻辑网络由包括节点，栅极和互连件的多个逻辑路径定义，包括在一个或多个计算机处将栅极尺寸分配给与其相邻的栅极 逻辑网络的定时路径端节点，基于门和互连延迟模型确定每个分配的门尺寸的性能/负载参数的n元组，​​以及确定两个或多个逻辑路径是否共享后代门。 共享后代门的两个或多个逻辑路径被耦合。 该方法还包括基于共享后代门的栅极大小，逐个递归地传播耦合的逻辑路径的n个元组，将沿着耦合逻辑路径的n元组的元组分组，检测是否 基于对二进制对参数的n元组的比较，并且消除所有耦合的逻辑路径中n个元组的任何一个n个元组，沿着耦合的 修剪与次佳箱相关的门尺寸的逻辑路径。

公开(公告)号：US06493854B1

公开(公告)日：2002-12-10

申请号：US09411725

申请日：1999-10-01

Applicant: Salim U. Chowdhury ,  David Ray Bearden

Inventor： Salim U. Chowdhury ,  David Ray Bearden

IPC: G06F1750

CPC classification number: G06F17/505

Abstract: A method of inserting repeaters into a network to improve timing characteristics of the network. Extraction and timing tools provide an RC network description and a slack report describing electrical and timing characteristics of a network. The timing characteristics include required arrival times of a signal generated at a source to each of the sinks of the network. A maximum slew rate is also defined at each of the sinks. Initial candidate locations for insertion of repeaters is determined. For a given set of legal repeater sizes, one or more sets of midvalue repeater sizes are determined which are used in successive approximation to identify actual repeater sizes to be considered at each of the candidate locations. At each candidate location, capacitance, required arrival time, and slew rate value (c, q, s) are determined in a bottom-up procedure. Suboptimal and invalid (c, q, s) choices at each candidate location are eliminated during successive iterations of the bottom-up procedure until the source node is reached. Further, one or more of the candidate locations are also eliminated. When the source device is reached, the (c, q, s) values are determined at the source for the given size of the source. The particular combination of (c, q, s) values at the descendant nodes relative to the source that provide a maximum q value at the source are selected, and this procedure is repeated in a top-down traversal to identify the best solution for the net for the particular repeater sizes being used.

Abstract translation: 将中继器插入网络以改善网络的定时特性的方法。 提取和定时工具提供了一个RC网络描述和一个描述网络的电气和时序特性的松散报告。 定时特性包括在源处产生的信号到网络的每个汇的所需到达时间。 每个汇点也定义最大压摆率。 确定插入中继器的初始候选位置。 对于给定的一组合法中继器大小，确定一组或多组中值中继器大小，其用于逐次逼近以识别在每个候选位置处要考虑的实际中继器大小。 在每个候选位置，电容，所需到达时间和转换速率值（c，q，s）在自下而上的过程中确定。 在自下而上的过程的连续迭代期间，消除了在每个候选位置处的次优和无效（c，q，s）选择，直到到达源节点。 此外，还消除了一个或多个候选位置。 当达到源设备时，在源的给定大小的源处确定（c，q，s）值。 选择在源处提供最大q值的相对于源的后代节点处的（c，q，s）值的特定组合，并且在自上而下的遍历中重复该过程，以确定最佳解决方案 用于所使用的特定中继器大小的网络。