CLFLUSH micro-architectural implementation method and system
    10.
    发明授权
    CLFLUSH micro-architectural implementation method and system 有权
    CLFLUSH微架构实现方法和系统

    公开(公告)号:US06546462B1

    公开(公告)日:2003-04-08

    申请号:US09475759

    申请日:1999-12-30

    IPC分类号: G06F1200

    CPC分类号: G06F12/0811 G06F12/0804

    摘要: A system and method for flushing a cache line associated with a linear memory address from all caches in the coherency domain. A cache controller receives a memory address, and determines whether the memory address is stored within the closest cache memory in the coherency domain. If a cache line stores the memory address, it is flushed from the cache. The flush instruction is allocated to a write-combining buffer within the cache controller. The write-combining buffer transmits the information to the bus controller. The bus controller locates instances of the memory address stored within external and intel cache memories within the coherency domain; these instances are flushed. The flush instruction can then be evicted from the write-combining buffer. Control bits may be used to indicate whether a write-combining buffer is allocated to the flush instruction, whether the memory address is stored within the closest cache memory, and whether the flush instruction should be evicted from the write-combining buffer.

    摘要翻译: 一种用于从一致性域中的所有高速缓存中刷新与线性存储器地址相关联的高速缓存行的系统和方法。 高速缓存控制器接收存储器地址,并且确定存储器地址是否存储在相干域中最接近的高速缓冲存储器中。 如果缓存行存储内存地址,则从缓存中刷新。 刷新指令被分配给高速缓存控制器内的写入组合缓冲器。 写合成缓冲器将信息发送到总线控制器。 总线控制器定位存储在相干域内的外部和英特尔高速缓存存储器中的存储器地址的实例; 这些实例被刷新。 然后可以从写入组合缓冲器中逐出驱动刷新指令。 控制位可以用于指示是否将写入组合缓冲器分配给闪存指令,存储器地址是否存储在最接近的高速缓冲存储器中,以及是否应该从写入组合缓冲器中驱逐刷新指令。