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1.发明授权Apparatus and method for speeding up access time of a large register file with wrap capability 有权用于加速具有包装能力的大型寄存器文件的访问时间的装置和方法公开(公告)号：US07243209B2
公开(公告)日：2007-07-10
申请号：US11044449
申请日：2005-01-27
CPC分类号： G06F9/30141 , G06F9/30098
摘要： An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.
摘要翻译： 提供了一种用于加速具有包装能力的大型寄存器文件的访问时间的装置和方法。 利用该装置和方法，从电路配置中消除了传统寄存器文件系统中的2：1多路复用器，而是提供了一半地址的附加主复用器，例如寄存器堆的前四个子阵列， 需要包装能力。 这些附加的主多路复用器接收读地址和移位的读字线信号。 另一个主复用器接收读地址和未移位的读字线信号。 来自移位和未移位的主复用器的输出被提供给一组次级多路复用器，它们将来自移位和未移位的主复用器的输出的比特复用以产生要由多个读/写寄存器堆使用的读地址 系统。
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2.发明授权Apparatus and method for providing multiple reads/writes using a 2Read/2Write register file array 有权使用2Read / 2Write寄存器文件阵列提供多次读/写的装置和方法公开(公告)号：US07663963B2
公开(公告)日：2010-02-16
申请号：US12134537
申请日：2008-06-06
IPC分类号： G11C8/00
CPC分类号： G06F9/30141
摘要： An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
摘要翻译： 提供一种用于读取多个连续条目并使用2Read / 2Write寄存器文件仅写入一个读取地址和一个写入地址的多个连续条目的装置和方法。 在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。 每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。 该装置和方法提供了通过仅对一个地址进行4到16个解码来写入连续条目的机制。 此外，该装置和方法提供了一种用于使用起始读字地址和基于起始读字地址生成的两个读字线从寄存器堆数组读取数据的机制。 两条读字线用于访问子阵列中条目的两个读端口。
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3.发明授权Method for providing multiple reads/writes using a 2read/2write register file array 有权使用2read / 2write寄存器文件阵列提供多次读/写的方法公开(公告)号：US07400548B2
公开(公告)日：2008-07-15
申请号：US11054276
申请日：2005-02-09
IPC分类号： G11C8/00
CPC分类号： G06F9/30141
摘要： Reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file is provided. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. A mechanism to write the consecutive entries by only having a 4 to 16 decode of one address is also provided. In addition, a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address is provided. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
摘要翻译： 提供了使用2Read / 2Write寄存器文件读取多个连续条目并且仅写入一个读取地址和一个写入地址的多个连续条目。 在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。 每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。 还提供了通过仅对一个地址进行4至16个解码来写入连续条目的机制。 此外，提供了一种用于使用起始读取字地址和基于起始读取字地址生成的两个读取字线从寄存器堆栈数据读取数据的机制。 两条读字线用于访问子阵列中条目的两个读端口。
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4.发明申请Apparatus and Method for Providing Multiple Reads/Writes Using a 2Read/2Write Register File Array 有权使用2Read / 2Write寄存器文件阵列提供多个读/写的装置和方法公开(公告)号：US20080239860A1
公开(公告)日：2008-10-02
申请号：US12134537
申请日：2008-06-06
IPC分类号： G11C8/00
CPC分类号： G06F9/30141
摘要： An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
摘要翻译： 提供一种用于读取多个连续条目并使用2Read / 2Write寄存器文件仅写入一个读取地址和一个写入地址的多个连续条目的装置和方法。 在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。 每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。 该装置和方法提供了通过仅对一个地址进行4到16个解码来写入连续条目的机制。 此外，该装置和方法提供了一种用于使用起始读字地址和基于起始读字地址生成的两个读字线从寄存器堆数组读取数据的机制。 两条读字线用于访问子阵列中条目的两个读端口。
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公开(公告)号：US08380964B2
公开(公告)日：2013-02-19
申请号：US12417878
申请日：2009-04-03
申请人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
发明人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
CPC分类号： G06F9/3855
摘要： An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update. The issue queue may selectively clock a row and a column of cells of the age matrix that correspond to a dispatched instruction's queue position while leaving other cells unclocked to conserve power.
摘要翻译： 信息处理系统包括具有可执行年龄跟踪操作的指令发布队列（IQ）的处理器。 问题队列IQ维护或存储可能在内部数据存储IDS中发出无序的指令。 IDS组织了队列位置（QPOS）寻址布置中的指令。 IQ的年龄矩阵维护IDS内的这些指令的相对指令老化记录。 年龄矩阵更新锁存器或其他存储单元数据，以反映在IQ调度操作期间IDS指令年龄的变化。 在发送一个或多个指令期间，年龄矩阵可以仅更新需要数据改变的锁存器以反映改变的IDS指令年龄。 年龄矩阵采用行和列数据和时钟控制来单独更新需要更新的锁存器。 问题队列可以选择性地对与分派指令的队列位置相对应的年龄矩阵的一行和一列单元进行计时，同时使其他单元不被锁定以节省功率。
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公开(公告)号：US20110185159A1
公开(公告)日：2011-07-28
申请号：US12417878
申请日：2009-04-03
申请人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
发明人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
IPC分类号： G06F9/312
CPC分类号： G06F9/3855
摘要： An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update. The issue queue may selectively clock a row and a column of cells of the age matrix that correspond to a dispatched instruction's queue position while leaving other cells unclocked to conserve power.
摘要翻译： 信息处理系统包括具有可执行年龄跟踪操作的指令发布队列（IQ）的处理器。 问题队列IQ维护或存储可能在内部数据存储IDS中发出无序的指令。 IDS组织了队列位置（QPOS）寻址布置中的指令。 IQ的年龄矩阵维护IDS内的这些指令的相对指令老化记录。 年龄矩阵更新锁存器或其他存储单元数据，以反映在IQ调度操作期间IDS指令年龄的变化。 在发送一个或多个指令期间，年龄矩阵可以仅更新需要数据改变的锁存器以反映改变的IDS指令年龄。 年龄矩阵采用行和列数据和时钟控制来单独更新需要更新的锁存器。 问题队列可以选择性地对与分派指令的队列位置相对应的年龄矩阵的一行和一列单元进行计时，同时使其他单元不被锁定以节省功率。
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公开(公告)号：US08489863B2
公开(公告)日：2013-07-16
申请号：US13451055
申请日：2012-04-19
申请人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
发明人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
CPC分类号： G06F9/3855
摘要： An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store (IDS). The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update.
摘要翻译： 信息处理系统包括具有可执行年龄跟踪操作的指令发布队列（IQ）的处理器。 问题队列IQ维护或存储可能在内部数据存储（IDS）中发出无序的指令。 IDS组织了队列位置（QPOS）寻址布置中的指令。 IQ的年龄矩阵维护IDS内的这些指令的相对指令老化记录。 年龄矩阵更新锁存器或其他存储单元数据，以反映在IQ调度操作期间IDS指令年龄的变化。 在发送一个或多个指令期间，年龄矩阵可以仅更新需要数据改变的锁存器以反映改变的IDS指令年龄。 年龄矩阵采用行和列数据和时钟控制来单独更新需要更新的锁存器。
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公开(公告)号：US20120260069A1
公开(公告)日：2012-10-11
申请号：US13451055
申请日：2012-04-19
申请人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
发明人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
IPC分类号： G06F9/30
CPC分类号： G06F9/3855
摘要： An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store (IDS). The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update.
摘要翻译： 信息处理系统包括具有可执行年龄跟踪操作的指令发布队列（IQ）的处理器。 问题队列IQ维护或存储可能在内部数据存储（IDS）中发出无序的指令。 IDS组织了队列位置（QPOS）寻址布置中的指令。 IQ的年龄矩阵维护IDS内的这些指令的相对指令老化记录。 年龄矩阵更新锁存器或其他存储单元数据，以反映在IQ调度操作期间IDS指令年龄的变化。 在发送一个或多个指令期间，年龄矩阵可以仅更新需要数据改变的锁存器以反映改变的IDS指令年龄。 年龄矩阵采用行和列数据和时钟控制来单独更新需要更新的锁存器。
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9.发明授权公开(公告)号：US07478276B2
公开(公告)日：2009-01-13
申请号：US11054988
申请日：2005-02-10
申请人： James Wilson Bishop , Hung Qui Le , Michael James Mack , Jafar Nahidi , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney , Brian William Thompto
发明人： James Wilson Bishop , Hung Qui Le , Michael James Mack , Jafar Nahidi , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney , Brian William Thompto
IPC分类号： G06F11/00
CPC分类号： G06F11/1407
摘要： A method and apparatus are provided for dispatch group checkpointing in a microprocessor, including provisions for handling partially completed dispatch groups and instructions which modify system coherent state prior to completion. An instruction checkpoint retry mechanism is implemented to recover from soft errors in logic. The processor is able to dispatch fixed point unit (FXU), load/store unit (LSU), and floating point unit (FPU) or vector multimedia extension (VMX) instructions on the same cycle. Store data is written to a store queue when a store instruction finishes executing. The data is held in the store queue until the store instruction is checkpointed, at which point it can be released to the coherently shared level 2 (L2) cache.
摘要翻译： 提供了一种用于微处理器中的调度组检查点的方法和装置，包括用于处理部分完成的调度组的规定以及在完成之前修改系统相干状态的指令。 执行指令检查点重试机制以从逻辑中的软错误中恢复。 处理器能够在同一周期内调度固定点单元（FXU），加载/存储单元（LSU）和浮点单元（FPU）或矢量多媒体扩展（VMX）指令。 存储指令完成执行时，存储数据将写入存储队列。 数据保存在存储队列中，直到存储指令检查点为止，此时可将数据释放到相干共享的级别2（L2）缓存。
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10.发明授权公开(公告)号：US07254697B2
公开(公告)日：2007-08-07
申请号：US11055831
申请日：2005-02-11
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/30149 , G06F9/382 , G06F9/3853
摘要： Dynamic reformatting of a dispatch group by selective activation of inactive Start bits of instructions within the dispatch group at the time the instructions are read from the IBUF. The number of instructions in the reformatted dispatch groups can vary from as few as one instruction per group to a maximum number of instructions read from the IBUF per cycle. The reformatted dispatch groupings can be terminated after a single cycle, or they can remain reformatted for as many cycles as desired, depending upon need.
摘要翻译： 通过在从IBUF读取指令时选择性地激活调度组内的非活动的开始位指令来动态重新格式化调度组。 重新格式化的调度组中的指令数量可以从每组少至一个指令变化到每个周期从IBUF读取的最大指令数。 重新格式化的调度分组可以在单个周期之后终止，或者根据需要，它们可以根据需要保持重新格式化多个周期。
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