公开(公告)号：US07478276B2

公开(公告)日：2009-01-13

申请号：US11054988

申请日：2005-02-10

申请人： James Wilson Bishop ,  Hung Qui Le ,  Michael James Mack ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney ,  Brian William Thompto

发明人： James Wilson Bishop ,  Hung Qui Le ,  Michael James Mack ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney ,  Brian William Thompto

IPC分类号： G06F11/00

CPC分类号： G06F11/1407

摘要： A method and apparatus are provided for dispatch group checkpointing in a microprocessor, including provisions for handling partially completed dispatch groups and instructions which modify system coherent state prior to completion. An instruction checkpoint retry mechanism is implemented to recover from soft errors in logic. The processor is able to dispatch fixed point unit (FXU), load/store unit (LSU), and floating point unit (FPU) or vector multimedia extension (VMX) instructions on the same cycle. Store data is written to a store queue when a store instruction finishes executing. The data is held in the store queue until the store instruction is checkpointed, at which point it can be released to the coherently shared level 2 (L2) cache.

摘要翻译： 提供了一种用于微处理器中的调度组检查点的方法和装置，包括用于处理部分完成的调度组的规定以及在完成之前修改系统相干状态的指令。 执行指令检查点重试机制以从逻辑中的软错误中恢复。 处理器能够在同一周期内调度固定点单元（FXU），加载/存储单元（LSU）和浮点单元（FPU）或矢量多媒体扩展（VMX）指令。 存储指令完成执行时，存储数据将写入存储队列。 数据保存在存储队列中，直到存储指令检查点为止，此时可将数据释放到相干共享的级别2（L2）缓存。

公开(公告)号：US07254697B2

公开(公告)日：2007-08-07

申请号：US11055831

申请日：2005-02-11

申请人： James Wilson Bishop ,  Hung Qui Le ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Brian William Thompto

发明人： James Wilson Bishop ,  Hung Qui Le ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/30149 ,  G06F9/382 ,  G06F9/3853

摘要： Dynamic reformatting of a dispatch group by selective activation of inactive Start bits of instructions within the dispatch group at the time the instructions are read from the IBUF. The number of instructions in the reformatted dispatch groups can vary from as few as one instruction per group to a maximum number of instructions read from the IBUF per cycle. The reformatted dispatch groupings can be terminated after a single cycle, or they can remain reformatted for as many cycles as desired, depending upon need.

摘要翻译： 通过在从IBUF读取指令时选择性地激活调度组内的非活动的开始位指令来动态重新格式化调度组。 重新格式化的调度组中的指令数量可以从每组少至一个指令变化到每个周期从IBUF读取的最大指令数。 重新格式化的调度分组可以在单个周期之后终止，或者根据需要，它们可以根据需要保持重新格式化多个周期。

公开(公告)号：US08418180B2

公开(公告)日：2013-04-09

申请号：US12129876

申请日：2008-05-30

申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/46

CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

摘要： A method, apparatus, and computer program product are disclosed for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles by selecting the first thread to be a primary thread and the second thread to be a secondary thread. If a condition exists that requires overriding, an override state is executed by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.

摘要翻译： 公开了一种用于确保同时多线程（SMT）微处理器中的处理公平性的方法，装置和计算机程序产品。 在通过选择作为主线程的第一线程和第二线程成为辅线程的持续期望的时钟周期数的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 如果存在需要覆盖的条件，则通过选择作为主线程的第二个线程和第一个线程作为辅助线程来执行覆盖状态。 超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。 响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

公开(公告)号：US07631308B2

公开(公告)日：2009-12-08

申请号：US11055850

申请日：2005-02-11

申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/46

CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

摘要： A method is disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread.

摘要翻译： 在数据处理系统中公开了一种用于确保在每个时钟周期期间同时执行多个线程的同时多线程（SMT）微处理器中的处理公平性的方法。 在持续预期数量的时钟周期的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 在标准选择状态期间，根据标准选择定义分配时钟周期优先级，通过在标准选择状态期间选择作为主线程的第一线程和第二线程作为次线程。 如果存在需要覆盖标准选择定义的条件，则执行超越状态，在该状态期间，通过选择第二个线程作为主线程，并将第一个线程作为次要线程来覆盖标准选择定义。

公开(公告)号：US20080294884A1

公开(公告)日：2008-11-27

申请号：US12129876

申请日：2008-05-30

申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/30

CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

摘要： A method, apparatus, and computer program product are disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.

摘要翻译： 在数据处理系统中公开了一种方法，装置和计算机程序产品，用于确保在每个时钟周期期间同时执行多个线程的同时多线程（SMT）微处理器中的处理公平性。 在持续预期数量的时钟周期的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 在标准选择状态期间，根据标准选择定义分配时钟周期优先级，通过在标准选择状态期间选择作为主线程的第一线程和第二线程作为次线程。 如果存在需要覆盖标准选择定义的条件，则执行超越状态，在该状态期间，通过选择第二个线程作为主线程，并将第一个线程作为次要线程来覆盖标准选择定义。 超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。 响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

公开(公告)号：US08489863B2

公开(公告)日：2013-07-16

申请号：US13451055

申请日：2012-04-19

申请人： James Wilson Bishop ,  Mary Douglass Brown ,  Jeffrey Carl Brownscheidle ,  Robert Allen Cordes ,  Maureen Anne Delaney ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Joel Abraham Silberman

发明人： James Wilson Bishop ,  Mary Douglass Brown ,  Jeffrey Carl Brownscheidle ,  Robert Allen Cordes ,  Maureen Anne Delaney ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Joel Abraham Silberman

IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40

CPC分类号： G06F9/3855

摘要： An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store (IDS). The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update.

摘要翻译： 信息处理系统包括具有可执行年龄跟踪操作的指令发布队列（IQ）的处理器。 问题队列IQ维护或存储可能在内部数据存储（IDS）中发出无序的指令。 IDS组织了队列位置（QPOS）寻址布置中的指令。 IQ的年龄矩阵维护IDS内的这些指令的相对指令老化记录。 年龄矩阵更新锁存器或其他存储单元数据，以反映在IQ调度操作期间IDS指令年龄的变化。 在发送一个或多个指令期间，年龄矩阵可以仅更新需要数据改变的锁存器以反映改变的IDS指令年龄。 年龄矩阵采用行和列数据和时钟控制来单独更新需要更新的锁存器。

公开(公告)号：US20120260069A1

公开(公告)日：2012-10-11

申请号：US13451055

申请日：2012-04-19

申请人： James Wilson Bishop ,  Mary Douglass Brown ,  Jeffrey Carl Brownscheidle ,  Robert Allen Cordes ,  Maureen Anne Delaney ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Joel Abraham Silberman

发明人： James Wilson Bishop ,  Mary Douglass Brown ,  Jeffrey Carl Brownscheidle ,  Robert Allen Cordes ,  Maureen Anne Delaney ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Joel Abraham Silberman

IPC分类号： G06F9/30

CPC分类号： G06F9/3855

摘要： An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store (IDS). The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update.

摘要翻译： 信息处理系统包括具有可执行年龄跟踪操作的指令发布队列（IQ）的处理器。 问题队列IQ维护或存储可能在内部数据存储（IDS）中发出无序的指令。 IDS组织了队列位置（QPOS）寻址布置中的指令。 IQ的年龄矩阵维护IDS内的这些指令的相对指令老化记录。 年龄矩阵更新锁存器或其他存储单元数据，以反映在IQ调度操作期间IDS指令年龄的变化。 在发送一个或多个指令期间，年龄矩阵可以仅更新需要数据改变的锁存器以反映改变的IDS指令年龄。 年龄矩阵采用行和列数据和时钟控制来单独更新需要更新的锁存器。

公开(公告)号：US08380964B2

公开(公告)日：2013-02-19

申请号：US12417878

申请日：2009-04-03

申请人： James Wilson Bishop ,  Mary Douglass Brown ,  Jeffrey Carl Brownscheidle ,  Robert Allen Cordes ,  Maureen Anne Delaney ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Joel Abraham Silberman

发明人： James Wilson Bishop ,  Mary Douglass Brown ,  Jeffrey Carl Brownscheidle ,  Robert Allen Cordes ,  Maureen Anne Delaney ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Joel Abraham Silberman

IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40

CPC分类号： G06F9/3855

摘要： An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update. The issue queue may selectively clock a row and a column of cells of the age matrix that correspond to a dispatched instruction's queue position while leaving other cells unclocked to conserve power.

摘要翻译： 信息处理系统包括具有可执行年龄跟踪操作的指令发布队列（IQ）的处理器。 问题队列IQ维护或存储可能在内部数据存储IDS中发出无序的指令。 IDS组织了队列位置（QPOS）寻址布置中的指令。 IQ的年龄矩阵维护IDS内的这些指令的相对指令老化记录。 年龄矩阵更新锁存器或其他存储单元数据，以反映在IQ调度操作期间IDS指令年龄的变化。 在发送一个或多个指令期间，年龄矩阵可以仅更新需要数据改变的锁存器以反映改变的IDS指令年龄。 年龄矩阵采用行和列数据和时钟控制来单独更新需要更新的锁存器。 问题队列可以选择性地对与分派指令的队列位置相对应的年龄矩阵的一行和一列单元进行计时，同时使其他单元不被锁定以节省功率。

公开(公告)号：US20110185159A1

公开(公告)日：2011-07-28

申请号：US12417878

申请日：2009-04-03

申请人： James Wilson Bishop ,  Mary Douglass Brown ,  Jeffrey Carl Brownscheidle ,  Robert Allen Cordes ,  Maureen Anne Delaney ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Joel Abraham Silberman

发明人： James Wilson Bishop ,  Mary Douglass Brown ,  Jeffrey Carl Brownscheidle ,  Robert Allen Cordes ,  Maureen Anne Delaney ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Joel Abraham Silberman

IPC分类号： G06F9/312

CPC分类号： G06F9/3855

摘要： An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update. The issue queue may selectively clock a row and a column of cells of the age matrix that correspond to a dispatched instruction's queue position while leaving other cells unclocked to conserve power.

摘要翻译： 信息处理系统包括具有可执行年龄跟踪操作的指令发布队列（IQ）的处理器。 问题队列IQ维护或存储可能在内部数据存储IDS中发出无序的指令。 IDS组织了队列位置（QPOS）寻址布置中的指令。 IQ的年龄矩阵维护IDS内的这些指令的相对指令老化记录。 年龄矩阵更新锁存器或其他存储单元数据，以反映在IQ调度操作期间IDS指令年龄的变化。 在发送一个或多个指令期间，年龄矩阵可以仅更新需要数据改变的锁存器以反映改变的IDS指令年龄。 年龄矩阵采用行和列数据和时钟控制来单独更新需要更新的锁存器。 问题队列可以选择性地对与分派指令的队列位置相对应的年龄矩阵的一行和一列单元进行计时，同时使其他单元不被锁定以节省功率。

公开(公告)号：US08108655B2

公开(公告)日：2012-01-31

申请号：US12410073

申请日：2009-03-24

申请人： Christopher Michael Abernathy ,  James Wilson Bishop ,  Mary Douglass Brown ,  William Elton Burky ,  Robert Allen Cordes ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Todd Alan Venton

发明人： Christopher Michael Abernathy ,  James Wilson Bishop ,  Mary Douglass Brown ,  William Elton Burky ,  Robert Allen Cordes ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Todd Alan Venton

IPC分类号： G06F9/302 ,  G06F9/312

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3885

摘要： Issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue. The simple fixed point instruction is a type of instruction that is executable by both a fixed point execution unit and a load-store execution unit. In turn, the issue logic determines that the unified payload does not include a load-store instruction that is ready to issue. As a result, the issue logic issues the simple fixed point instruction to the load-store execution unit in response to determining that the simple fixed point instruction is ready to issue and determining that the unified payload does not include a load-store instruction that is ready to issue.

摘要翻译： 问题逻辑标识一个简单的固定点指令，包含在一个准备发布的统一有效载荷中。 简单的固定点指令是一种可由固定点执行单元和加载存储执行单元执行的指令。 反过来，问题逻辑确定统一有效载荷不包括准备发布的加载存储指令。 结果，响应于确定简单的固定点指令准备发出并且确定统一的有效载荷不包括加载存储指令，问题逻辑将简单的固定点指令发布到加载存储执行单元 准备发行。