公开(公告)号：US20250104632A1

公开(公告)日：2025-03-27

申请号：US18890456

申请日：2024-09-19

Applicant: Samsung Display Co., LTD.

Inventor： KEUK-JIN JEONG ,  WONGYUN KIM ,  JIHOON YANG ,  MIN KANG

IPC: G09G3/3233 ,  G09G3/32

Abstract: A pixel circuit includes a light emitting element including an anode electrode and a cathode electrode, a driving transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, a data write transistor including a gate electrode, a first electrode, and a second electrode connected to the second node, a compensation transistor including a gate electrode, a first electrode connected to the third node, and a second electrode connected to the first node, an initialization transistor including a gate electrode, a first electrode, and a second electrode connected to the first node, a first light emission control transistor including a gate electrode, a first electrode, and a second electrode connected to the second node, and a storage capacitor including a first electrode and a second electrode connected to the first node.

公开(公告)号：US20170263177A1

公开(公告)日：2017-09-14

申请号：US15447748

申请日：2017-03-02

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： CHOLHO KIM ,  GUNWOO YANG ,  JIHOON YANG ,  YONGWOO LEE ,  HYUNYOUNG CHOI

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/28

Abstract: An N-th stage of a gate driver includes a first control circuit, a gate signal generating circuit, a carry signal generating circuit, a second control circuit, a third control circuit, and a holding circuit. The first control circuit controls a first signal in response to a first input signal. The gate signal generating circuit generates a gate signal in response to a clock signal and the first signal. The carry signal generating circuit generates a carry signal in response to the clock signal and the first signal. The second control circuit controls the first signal in response to a second input signal. The third control circuit generates a hold control signal in response to a third input signal having a frequency lower than the clock signal's. The holding circuit maintains levels of the first signal, the gate signal, and the carry signal in response to the hold control signal.

公开(公告)号：US20250140198A1

公开(公告)日：2025-05-01

申请号：US18919448

申请日：2024-10-18

Applicant: Samsung Display Co., Ltd.

Inventor： JUNGHWAN HWANG ,  DONGWOO KIM ,  JIHOON YANG ,  HYUNJOON KIM

IPC: G09G3/3258

Abstract: A driver including multiple stages is disclosed. At least one of the stages includes an input circuit configured to transfer an input signal to a first node in response to a clock signal, a first transistor connected between the first node and a second node, a carry circuit configured to output a carry signal having a first high gate voltage when the second node has the first high gate voltage, and a level shifting output circuit configured to output an output signal having a second high gate voltage higher than the first high gate voltage by level-shifting the first high gate voltage of the second node.

公开(公告)号：US20250048835A1

公开(公告)日：2025-02-06

申请号：US18653744

申请日：2024-05-02

Applicant: Samsung Display Co., Ltd.

Inventor： JIHOON YANG ,  MIN KANG ,  JUNG SUK BANG ,  CHEOL-GON LEE

IPC: H10K59/121 ,  H10K59/131 ,  H10K59/65

Abstract: A display device includes a first control line, a second control line, and a third control line arranged in a first direction, the first control line being between the second control line and the third control line, a pixel circuit coupled to the first control line, the second control line, and the third control line, a light-emitting element coupled to the pixel circuit, a sensor circuit coupled to the first control line, and having a first connection node between the first control line and the third control line, a light-receiving element coupled to the sensor circuit, and a receive line coupled to the first connection node of the sensor circuit.

公开(公告)号：US20230005412A1

公开(公告)日：2023-01-05

申请号：US17931311

申请日：2022-09-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： CHOLHO KIM ,  GUNWOO YANG ,  HYUNYOUNG CHOI ,  JIHOON YANG ,  YONGWOO LEE

IPC: G09G3/20 ,  G11C19/28 ,  G09G3/36 ,  G09G3/3266

Abstract: A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.

公开(公告)号：US20170249893A1

公开(公告)日：2017-08-31

申请号：US15412691

申请日：2017-01-23

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： CHOLHO KIM ,  GUNWOO YANG ,  HYUNYOUNG CHOI ,  JIHOON YANG ,  YONGWOO LEE

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0223 ,  G11C19/28

Abstract: A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.