公开(公告)号：US20140375616A1

公开(公告)日：2014-12-25

申请号：US14067663

申请日：2013-10-30

Applicant: Samsung Display Co., LTD

Inventor： Ji-Hye KIM ,  Seung-Kyu LEE ,  Ki-Myeong EOM

IPC: G09G3/32

CPC classification number: G09G3/3266 ,  G09G3/3275 ,  G09G3/3611 ,  G09G3/3674 ,  G09G2310/0286

Abstract: A stage circuit including a plurality of stages connected to each other, where each of the stages includes: an output unit configured to output a voltage of a first power source or a signal of a third input terminal to an output terminal, based on a voltage applied to a first node or a second node; a first driver configured to control a voltage at a third node, based on signals of a first input terminal, a second input terminal and the third input terminal; a second driver configured to control the voltage at the first node, based on the signal of the second input terminal and the voltage at the third node; and a first transistor connected between the second node and the third node and maintained in a turn-on state.

Abstract translation: 一种级联电路，包括彼此连接的多个级，其中每个级包括：输出单元，其被配置为基于电压将电压或第三输入端子的信号输出到输出端子 应用于第一节点或第二节点; 第一驱动器，被配置为基于第一输入端子，第二输入端子和第三输入端子的信号来控制第三节点处的电压; 第二驱动器，被配置为基于第二输入端子的信号和第三节点处的电压来控制第一节点处的电压; 以及连接在第二节点和第三节点之间并保持在导通状态的第一晶体管。

公开(公告)号：US20170287404A1

公开(公告)日：2017-10-05

申请号：US15458668

申请日：2017-03-14

Applicant: Samsung Display Co., LTD.

Inventor： Ji-Hye KIM ,  Min-Kyu WOO

IPC: G09G3/3266 ,  G09G3/3291

CPC classification number: G09G3/3266 ,  G09G3/20 ,  G09G3/3233 ,  G09G3/3291 ,  G09G2300/0426 ,  G09G2300/0861 ,  G09G2300/0871 ,  G09G2310/0278 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0291 ,  G11C19/28

Abstract: A scan driver may include a first stage, a second stage, and a third stage. The first stage may include a first output transistor. The first output transistor may have a first buffer value. The second stage may be electrically connected to the first output transistor and may include a second output transistor. The second output transistor may have a second buffer value. The third stage may be electrically connected to the second output transistor and may include a third output transistor. The third output transistor may have a third buffer value. At least one of the second buffer value and the third buffer value may be unequal to the first buffer value.

公开(公告)号：US20150102312A1

公开(公告)日：2015-04-16

申请号：US14445286

申请日：2014-07-29

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jae-Sic LEE ,  Ji-Hye KIM ,  Dong-Wook KIM ,  Tae-Gon KIM

IPC: H01L27/32 ,  H01L23/48 ,  G09G3/32

CPC classification number: H01L27/3223 ,  G09G3/3233 ,  G09G2300/0413 ,  G09G2300/0842 ,  G09G2330/08 ,  G09G2330/10 ,  H01L27/3276 ,  H01L2251/568

Abstract: A display apparatus includes an array of pixels and dummy pixels. A plurality of first lines are connected to the pixels and the dummy pixels. A plurality of repair lines are connected to the dummy pixels and are selectively connected to the pixels. A plurality of second lines are connected to the pixels. At least one dummy line is connected to the dummy pixels. At least one dummy wiring is connected to the at least one dummy line and is selectively connected to one of the second lines.

Abstract translation: 显示装置包括像素阵列和虚拟像素。 多个第一行连接到像素和虚拟像素。 多个修复线连接到虚拟像素并且选择性地连接到像素。 多个第二线连接到像素。 至少一个虚拟线连接到虚拟像素。 至少一个虚拟布线连接到至少一个虚拟线，并且选择性地连接到第二条线之一。