公开(公告)号：US11100847B2

公开(公告)日：2021-08-24

申请号：US16781187

申请日：2020-02-04

Applicant: Samsung Display Co., Ltd.

Inventor： Yang Hwa Choi ,  Sun Kwang Kim ,  Sang Jin Jeon

IPC: G09G3/32

Abstract: A scan driver includes two or more scan signal output circuits (SSOC), each being coupled to a first scan line (FSL) and a second scan line (SSL), and including a driving circuit, a first buffer circuit (FBC), and a second buffer circuit (SBC). The driving circuit applies a first driving signal (DS) to a first driving node (DN) and applies a second DS to a second DN based on an input signal, a clock signal (CS), a display-on signal, and an on-level voltage. The input signal is a scan start signal or a previous scan signal. The FBC outputs a sensing signal to the SSL based on the first DS, the second DS, an off-level voltage, and a sensing CS. The SBC outputs a scan signal to the FSL based on the first DS, the second DS, the off-level voltage, and a scan CS.

公开(公告)号：US10706784B2

公开(公告)日：2020-07-07

申请号：US15950516

申请日：2018-04-11

Applicant: Samsung Display Co., Ltd.

Inventor： Sung Hwan Kim ,  Bon Yong Koo ,  Sun Kwang Kim ,  Chong Chul Chai

IPC: G09G3/3266 ,  G09G3/36

Abstract: A stage circuit includes an output circuit configured to supply, to a first output terminal, a first clock signal supplied to a second input terminal or to supply a voltage of a second power source supplied to a second power input terminal, in response to voltages of a first node and a second node, an input circuit configured to control voltages of a third node and a fourth node in response to a shift pulse or a gate start pulse supplied to a first input terminal, a third clock signal supplied to a third input terminal, and a fourth clock signal supplied to a fourth input terminal, and a first driver configured to control the voltages of the first and second nodes in response to both the third clock signal and the voltages of the third and fourth nodes.

公开(公告)号：US10147777B2

公开(公告)日：2018-12-04

申请号：US15666307

申请日：2017-08-01

Applicant: Samsung Display Co., Ltd.

Inventor： Bek Hyun Lim ,  Ki Nyeng Kang ,  Jin Koo Kang ,  Sun Kwang Kim

IPC: H01L27/32 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3275 ,  H01L27/12

Abstract: A display device includes: a circuit part including at least one first region and at least one second region disposed adjacent to the first region, wherein the second region includes first pixel circuits arranged adjacent to the first region and second pixel circuits spaced apart from the first region; a display element part disposed on the circuit part, wherein a first display elements are connected to the first pixel circuits and overlap with the first region, and a second display elements are connected to the second pixel circuits; and bridge patterns electrically connecting the first and second pixel circuits and the first and second display elements, wherein the length of bridge patterns connecting the first pixel circuits and the first display elements is different from that of bridge patterns connecting the second pixel circuits and the second display elements.

公开(公告)号：US11552154B2

公开(公告)日：2023-01-10

申请号：US16915532

申请日：2020-06-29

Applicant: Samsung Display Co., LTD.

Inventor： Sang Hoon Lee ,  Ki Nyeng Kang ,  Sun Kwang Kim ,  Tae Woo Kim ,  Jong Hyun Choi ,  Tae Hoon Yang

IPC: H01L29/08 ,  H01L27/32

Abstract: A display device includes a substrate including a display area including pixels, and a light transmissive area including a portion in the display area, and signal lines disposed in the display area and electrically connected with the pixels, where the signal lines include a first signal line on a first side, a second signal line on a second side and arranged with the first signal line in a first direction, and a third signal line on a third side, and the third signal line is arranged with the first signal line and the second signal line in a second direction, the first and second signal lines are insulated from each other in the display area, and a length of the first signal line is longer than a length of the second signal line in the first direction.

公开(公告)号：US11164533B2

公开(公告)日：2021-11-02

申请号：US17093876

申请日：2020-11-10

Applicant: Samsung Display Co. Ltd.

Inventor： Jun Hyun Park ,  Sun Kwang Kim ,  Young Wan Seo ,  Cheol Gon Lee ,  Yang Hwa Choi

IPC: G09G3/3291 ,  G09G3/3258 ,  G09G3/3233 ,  G09G3/3266

Abstract: A display device includes a data line to which a data voltage is applied, a first driving voltage line to which a first driving voltage is applied, a second driving voltage line to which a second driving voltage is applied, and a pixel connected to the first and second driving voltage lines. The pixel includes a first transistor to control a driving current according to a voltage applied to a first node, a light emitting element between the first transistor and the first driving voltage line, and a capacitor between the first node and the second driving voltage line. The first driving voltage has a first high-level voltage during a first initialization period, the first driving voltage has a first mid-level voltage lower than the first high level voltage during a threshold-voltage-storage period, and the first driving voltage has a first low-level voltage during a second initialization period.

公开(公告)号：US20240315094A1

公开(公告)日：2024-09-19

申请号：US18122245

申请日：2023-03-16

Applicant: Samsung Display Co., LTD.

Inventor： Sun Kwang Kim ,  Ki Nyeng Kang ,  Yoo Mi Ra ,  Kyung-Ho Park ,  Hyungjin Song ,  Kye Uk Lee ,  Hwan Young Jang

IPC: H10K59/131

CPC classification number: H10K59/131 ,  G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0842

Abstract: A display device includes: a substrate; a first conductive layer disposed on the substrate and including a data line, an initialization voltage line, and a driving voltage line; and a semiconductor layer disposed on the first conductive layer. The semiconductor layer includes a first semiconductor, a second semiconductor, and a third semiconductor spaced apart from each other, the first semiconductor is electrically connected to the driving voltage line, the second semiconductor is electrically connected to the data line, the third semiconductor is electrically connected to the initialization voltage line, and the second semiconductor does not overlap the data line in a direction perpendicular to a surface of the substrate.

公开(公告)号：US12069917B2

公开(公告)日：2024-08-20

申请号：US18083807

申请日：2022-12-19

Applicant: Samsung Display Co., LTD.

Inventor： Sang Hoon Lee ,  Ki Nyeng Kang ,  Sun Kwang Kim ,  Tae Woo Kim ,  Jong Hyun Choi ,  Tae Hoon Yang

IPC: H01L29/08 ,  H10K59/121 ,  H10K59/131

CPC classification number: H10K59/131 ,  H10K59/1213

Abstract: A display device includes a substrate including a display area including pixels, and a light transmissive area including a portion in the display area, and signal lines disposed in the display area and electrically connected with the pixels, where the signal lines include a first signal line on a first side, a second signal line on a second side and arranged with the first signal line in a first direction, and a third signal line on a third side, and the third signal line is arranged with the first signal line and the second signal line in a second direction, the first and second signal lines are insulated from each other in the display area, and a length of the third signal line is longer than a length of the second signal line in the first direction.

公开(公告)号：US20210383748A1

公开(公告)日：2021-12-09

申请号：US17409707

申请日：2021-08-23

Applicant: Samsung Display Co., Ltd.

Inventor： Yang Hwa CHOI ,  Sun Kwang Kim ,  Sang Jin JEON

IPC: G09G3/32

Abstract: A scan driver includes two or more scan signal output circuits (SSOC), each being coupled to a first scan line (FSL) and a second scan line (SSL), and including a driving circuit, a first buffer circuit (FBC), and a second buffer circuit (SBC). The driving circuit applies a first driving signal (DS) to a first driving node (DN) and applies a second DS to a second DN based on an input signal, a clock signal (CS), a display-on signal, and an on-level voltage. The input signal is a scan start signal or a previous scan signal. The FBC outputs a sensing signal to the SSL based on the first DS, the second DS, an off-level voltage, and a sensing CS. The SBC outputs a scan signal to the FSL based on the first DS, the second DS, the off-level voltage, and a scan CS.

公开(公告)号：US11004376B2

公开(公告)日：2021-05-11

申请号：US16680414

申请日：2019-11-11

Applicant: Samsung Display Co., Ltd.

Inventor： Yang Hwa Choi ,  Sun Kwang Kim ,  Sang Jin Jeon

IPC: G09G3/32 ,  G09G3/20

Abstract: A scan driver for a display device includes scan signal output circuits connected to each other through scan lines. Each scan signal output circuit includes: a drive circuit to apply a first drive signal to a first drive node, to apply a second drive signal to a second drive node, and to apply a connection signal to a connection signal output node based on i) an input signal which is one of either a scan start signal or a scan signal applied by another scan signal output circuit, ii) a clock signal, and iii) an on-level voltage; and a buffer circuit to receive the connection signal, the first drive signal, and the second drive signal from the drive circuit, and to output one of scan signals to one of the scan lines based on the first drive signal, the second drive signal, and the clock signal.

公开(公告)号：US20210082353A1

公开(公告)日：2021-03-18

申请号：US17093876

申请日：2020-11-10

Applicant: Samsung Display Co. Ltd.

Inventor： Jun Hyun Park ,  Sun Kwang Kim ,  Young Wan Seo ,  Cheol Gon Lee ,  Yang Hwa Choi

IPC: G09G3/3291 ,  G09G3/3258 ,  G09G3/3233 ,  G09G3/3266

Abstract: A display device includes a data line to which a data voltage is applied, a first driving voltage line to which a first driving voltage is applied, a second driving voltage line to which a second driving voltage is applied, and a pixel connected to the first and second driving voltage lines. The pixel includes a first transistor to control a driving current according to a voltage applied to a first node, a light emitting element between the first transistor and the first driving voltage line, and a capacitor between the first node and the second driving voltage line. The first driving voltage has a first high-level voltage during a first initialization period, the first driving voltage has a first mid-level voltage lower than the first high level voltage during a threshold-voltage-storage period, and the first driving voltage has a first low-level voltage during a second initialization period.