公开(公告)号：US20240412693A1

公开(公告)日：2024-12-12

申请号：US18809281

申请日：2024-08-19

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： WONJUN LEE ,  CHOLHO KIM ,  MIHYEON JO

IPC: G09G3/3233 ,  G06V40/13

Abstract: A display device includes a plurality of pixels, each of which includes a light emitting element and a pixel driving circuit and a plurality of sensors, each of which includes a light receiving element and a sensor driving circuit. The sensor driving circuit includes a first reset transistor, a second reset transistor, a sensing capacitor, an amplification transistor, and an output transistor. The first reset transistor includes a first electrode receiving a reset voltage, a second electrode connected to a first sensing node, and a third electrode receiving a reset control signal. The second reset transistor includes a first electrode receiving the reset voltage, a second electrode connected to a second sensing node, and a third electrode receiving the reset control signal. The sensing capacitor is positioned between the first sensing node and the second sensing node.

公开(公告)号：US20170263177A1

公开(公告)日：2017-09-14

申请号：US15447748

申请日：2017-03-02

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： CHOLHO KIM ,  GUNWOO YANG ,  JIHOON YANG ,  YONGWOO LEE ,  HYUNYOUNG CHOI

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/28

Abstract: An N-th stage of a gate driver includes a first control circuit, a gate signal generating circuit, a carry signal generating circuit, a second control circuit, a third control circuit, and a holding circuit. The first control circuit controls a first signal in response to a first input signal. The gate signal generating circuit generates a gate signal in response to a clock signal and the first signal. The carry signal generating circuit generates a carry signal in response to the clock signal and the first signal. The second control circuit controls the first signal in response to a second input signal. The third control circuit generates a hold control signal in response to a third input signal having a frequency lower than the clock signal's. The holding circuit maintains levels of the first signal, the gate signal, and the carry signal in response to the hold control signal.

公开(公告)号：US20230215365A1

公开(公告)日：2023-07-06

申请号：US18085260

申请日：2022-12-20

Applicant: Samsung Display Co., Ltd.

Inventor： WONJUN LEE ,  CHOLHO KIM ,  MIHYEON JO

IPC: G09G3/3233 ,  G06V40/13

CPC classification number: G09G3/3233 ,  G06V40/1318 ,  G09G2300/0842 ,  G09G2300/0819 ,  G09G2310/08 ,  G09G2300/0426 ,  G09G2354/00

Abstract: A display device includes a plurality of pixels, each of which includes a light emitting element and a pixel driving circuit and a plurality of sensors, each of which includes a light receiving element and a sensor driving circuit. The sensor driving circuit includes a first reset transistor, a second reset transistor, a sensing capacitor, an amplification transistor, and an output transistor. The first reset transistor includes a first electrode receiving a reset voltage, a second electrode connected to a first sensing node, and a third electrode receiving a reset control signal. The second reset transistor includes a first electrode receiving the reset voltage, a second electrode connected to a second sensing node, and a third electrode receiving the reset control signal. The sensing capacitor is positioned between the first sensing node and the second sensing node.

公开(公告)号：US20230005412A1

公开(公告)日：2023-01-05

申请号：US17931311

申请日：2022-09-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： CHOLHO KIM ,  GUNWOO YANG ,  HYUNYOUNG CHOI ,  JIHOON YANG ,  YONGWOO LEE

IPC: G09G3/20 ,  G11C19/28 ,  G09G3/36 ,  G09G3/3266

Abstract: A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.

公开(公告)号：US20170249893A1

公开(公告)日：2017-08-31

申请号：US15412691

申请日：2017-01-23

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： CHOLHO KIM ,  GUNWOO YANG ,  HYUNYOUNG CHOI ,  JIHOON YANG ,  YONGWOO LEE

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0223 ,  G11C19/28

Abstract: A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.