公开(公告)号：US20170179158A1

公开(公告)日：2017-06-22

申请号：US15344084

申请日：2016-11-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： SANG KYUNG LEE ,  SANG-HO MOON

IPC: H01L27/12 ,  H01L21/44 ,  H01L29/786 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L27/124 ,  H01L21/44 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78648 ,  H01L29/7869

Abstract: A transistor array panel includes a transistor disposed on a substrate. The transistor includes a gate electrode, a source electrode, a drain electrode, a semiconductor, and a top electrode. The top electrode is disposed on and overlaps the semiconductor, and is electrically connected to the source electrode.

公开(公告)号：US20220190078A1

公开(公告)日：2022-06-16

申请号：US17512926

申请日：2021-10-28

Applicant: Samsung Display Co., Ltd.

Inventor： CHUNGI YOU ,  SANG-HO MOON

IPC: H01L27/32 ,  H01L51/56 ,  H01L51/52

Abstract: A method of manufacturing a display device may include forming an active pattern on a substrate, the active pattern including a first region, a second region spaced apart from the first region, and a third region disposed between the first region and the second region, forming an insulation layer on the active pattern, defining a first contact hole exposing a portion of the first region, a second contact hole exposing a portion of the second region, and an opening exposing the third region in the insulation layer, forming a conductive pattern filling the first and second contact holes on the insulation layer and removing the third region at a substantially same time, and forming a planarization layer on the conductive pattern.