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公开(公告)号：US20180211602A1
公开(公告)日：2018-07-26
申请号：US15827461
申请日：2017-11-30
Applicant: Samsung Display Co., Ltd.
Inventor： Dong Beom CHO , Hee Bum PARK , Song Yi HAN
IPC: G09G3/3258 , G09G3/36
CPC classification number: G09G3/3258 , G09G3/3233 , G09G3/3607 , G09G2310/0248 , G09G2310/0264 , G09G2310/08
Abstract: A display device includes: a timing controller to provide data including a pre-emphasis value and an image data value; a gamma reference voltage supplier to selectively supply one of a first gamma reference voltage and a second gamma reference voltage different from the first gamma reference voltage; and a data driver to supply a pre-emphasis voltage, that is generated based on the pre-emphasis value and the first gamma reference voltage, to data lines during a first period of a horizontal period, and to supply a data voltage, that is generated based on the image data value and the second gamma reference voltage, to the data lines during a second period of the horizontal period. The timing controller is to control the gamma reference voltage supplier to supply the first gamma reference voltage during the first period and to supply the second gamma reference voltage during the second period.
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公开(公告)号：US20180233105A1
公开(公告)日：2018-08-16
申请号：US15786118
申请日：2017-10-17
Applicant: Samsung Display Co. Ltd.
Inventor： Dong Beom CHO , Hee Bum PARK , Dae Sik LEE , Song Yi HAN
CPC classification number: G09G5/008 , G09G3/2003 , G09G3/204 , G09G3/2096 , G09G3/3266 , G09G3/3677 , G09G3/3696 , G09G5/18 , G09G2300/0426 , G09G2310/0267 , G09G2310/0272 , G09G2310/0289 , G09G2370/08
Abstract: A display device includes a display panel including a plurality of pixels which are connected to a plurality of gate lines and a plurality of data lines and display a plurality of consecutive frames of images, a data driver driving the data lines, a gate driver driving the gate lines, a clock generator outputting a gate clock signal, which drives the gate driver and swings between a gate-on voltage and a gate-off voltage, and a signal controller outputting a gate pulse signal which drives the clock generator and a data control signal which controls the data driver. The clock generator includes a voltage maintainer maintaining the gate clock signal at a reference voltage that has a fixed value between the gate-on voltage and the gate-off voltage for a predetermined time.
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公开(公告)号：US20230169934A1
公开(公告)日：2023-06-01
申请号：US18100971
申请日：2023-01-24
Applicant: Samsung Display Co., Ltd.
Inventor： Dong Beom CHO , Hee Bum PARK , Dae Sik LEE , Song Yi HAN
CPC classification number: G09G5/008 , G09G3/204 , G09G3/2003 , G09G3/2096 , G09G3/3696 , G09G5/18 , G09G3/3266 , G09G2300/0426 , G09G2310/0267 , G09G2310/0272 , G09G2310/0289 , G09G2370/08
Abstract: A display device includes a display panel including a plurality of pixels which are connected to a plurality of gate lines and a plurality of data lines and display a plurality of consecutive frames of images, a data driver driving the data lines, a gate driver driving the gate lines, a clock generator outputting a gate clock signal, which drives the gate driver and swings between a gate-on voltage and a gate-off voltage, and a signal controller outputting a gate pulse signal which drives the clock generator and a data control signal which controls the data driver. The clock generator includes a voltage maintainer maintaining the gate clock signal at a reference voltage that has a fixed value between the gate-on voltage and the gate-off voltage for a predetermined time.
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公开(公告)号：US20210118402A1
公开(公告)日：2021-04-22
申请号：US17132936
申请日：2020-12-23
Applicant: Samsung Display Co., Ltd.
Inventor： Dong Beom CHO , Hee Bum PARK , Dae Sik LEE , Song Yi HAN
Abstract: A display device includes a display panel including a plurality of pixels which are connected to a plurality of gate lines and a plurality of data lines and display a plurality of consecutive frames of images, a data driver driving the data lines, a gate driver driving the gate lines, a clock generator outputting a gate clock signal, which drives the gate driver and swings between a gate-on voltage and a gate-off voltage, and a signal controller outputting a gate pulse signal which drives the clock generator and a data control signal which controls the data driver. The clock generator includes a voltage maintainer maintaining the gate clock signal at a reference voltage that has a fixed value between the gate-on voltage and the gate-off voltage for a predetermined time.
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