公开(公告)号：US20240096717A1

公开(公告)日：2024-03-21

申请号：US18213386

申请日：2023-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： AE-NEE JANG ,  SEUNGDUK BAEK

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L22/32 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/08113 ,  H01L2224/08148 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1435

Abstract: A semiconductor package includes a first semiconductor chip on a substrate and including a first semiconductor substrate and a first test pattern on a first surface of the first semiconductor substrate, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor substrate and a second test pattern on a second surface of the second semiconductor substrate. The first and second semiconductor chips bonded to allow the first test pattern to face the second test pattern. The first test pattern includes a first in-pad, first connection pads, and a first out-pad. The second test pattern includes a second in-pad bonded to the first in-pad, a second out-pad bonded to the first out-pad, and second connection pads bonded to the first connection pads. The first and second connection pads are connected in series to alternately connect with each other and form a series wiring pattern, so that each first connection pad connects to another first connection pad in one direction along the series wiring pattern and to a second connection pad in an opposite direction along the series wiring pattern.

公开(公告)号：US20220208730A1

公开(公告)日：2022-06-30

申请号：US17454114

申请日：2021-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： AE-NEE JANG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes a plurality of first semiconductor structures that are stacked on a package substrate and are offset from each other in a first direction, and a plurality of first adhesive layers disposed between the first semiconductor structures. Each of the first semiconductor structures includes a first sub-chip and a second sub-chip in contact with a part of a top surface of the first sub-chip. The first adhesive layers are disposed between and are in contact with the first sub-chips. The first adhesive layers are spaced apart from the second sub-chips. A thickness of each of the first adhesive layers is less than a thickness of each of the second sub-chips. The thickness of the second sub-chip is in a range of about 13 μm to about 20 μm.

公开(公告)号：US20250158002A1

公开(公告)日：2025-05-15

申请号：US18939655

申请日：2024-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： AE-NEE JANG ,  Haseob SEONG

IPC: H01L25/18 ,  H01L23/00 ,  H10B80/00

Abstract: A semiconductor package may include a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip may include upper bonding pads in an upper portion thereof, and the second semiconductor chip may include lower bonding pads in a lower portion thereof. The first semiconductor chip and the second semiconductor chip may be connected to each other by the upper bonding pads and the lower bonding pads, which are in direct contact with each other. The upper bonding pads may include a first pad, a dummy pad, and a second pad, which are arranged to be adjacent to each other in a first direction, and the first pads and the second pads are configured to be applied with voltages of different levels from each other.

公开(公告)号：US20220149013A1

公开(公告)日：2022-05-12

申请号：US17582079

申请日：2022-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： AE-NEE JANG ,  YOUNG LYONG KIM

IPC: H01L25/065 ,  H01L23/31

Abstract: Semiconductor devices may include a first semiconductor chip, a first redistribution layer on a bottom surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a second redistribution layer on a bottom surface of the second semiconductor chip, a mold layer extending on sidewalls of the first and second semiconductor chips and on the bottom surface of the first semiconductor chip, and an external terminal extending through the mold layer and electrically connected to the first redistribution layer. The second redistribution layer may include an exposed portion. The first redistribution layer may include a first conductive pattern electrically connected to the first semiconductor chip and a second conductive pattern electrically insulated from the first semiconductor chip. The exposed portion of the second redistribution layer and the second conductive pattern of the first redistribution layer may be electrically connected by a first connection wire.

公开(公告)号：US20250157962A1

公开(公告)日：2025-05-15

申请号：US18761918

申请日：2024-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HANSUNG RYU ,  JONGBEOM PARK ,  HASEOB SEONG ,  AE-NEE JANG ,  JEEHYUN JUNG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes: a plurality of first semiconductor chips; a second semiconductor chip including a front surface and disposed on the plurality of first semiconductor chips, and wherein the second semiconductor chip further includes a first dummy pad located on a back surface thereof; and a third semiconductor chip including a front surface and disposed on the second semiconductor chip. The third semiconductor chip further includes a second dummy pad located on the front surface thereof. The first dummy pad is disposed on at least a part of a back surface edge region that is adjacent to a side surface of the second semiconductor chip. The second dummy pad is disposed on at least a part of a front surface edge region that is adjacent to a side surface of the third semiconductor chip. The first dummy pad and the second dummy pad are bonded to each other.

公开(公告)号：US20210183724A1

公开(公告)日：2021-06-17

申请号：US16994938

申请日：2020-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SHLE-GE LEE ,  Youngbae Kim ,  AE-NEE JANG

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/528 ,  H01L23/00

Abstract: A semiconductor module includes a substrate having a central region, an outer region that surrounds the central region, and a middle region disposed between the central and the outer region, a first semiconductor package mounted on the central region of the substrate, a plurality of second semiconductor packages mounted on the middle region of the substrate, and a heat radiation structure disposed on the first semiconductor package and second semiconductor packages. The heat radiation structure includes a first part that is disposed on top surfaces of the first and second semiconductor packages, a second part that surrounds the middle region, a third part that is spaced apart from the second part and surrounds the first semiconductor package, and a fourth part that connects the second part to the third part.