公开(公告)号：US20150058692A1

公开(公告)日：2015-02-26

申请号：US14334947

申请日：2014-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Amir BENNATAN ,  Avner DOR ,  Moshe TWITTO ,  Guy GABSO ,  Yoav SHERESHEVSKI ,  Uri BEITLER ,  Jun-jin KONG ,  Beom-Kyu SHIN

IPC: H03M13/11

CPC classification number: H03M13/1111 ,  G11B2020/185 ,  H03M13/1131 ,  H03M13/1137 ,  H03M13/6566

Abstract: A low-density parity-check (LDPC) decoding method includes exchanging messages between check nodes and variable nodes based on scheduling information representing an order of exchanging messages between the check nodes and the variable nodes for an LDPC decoding, and performing the LDPC decoding based on the exchanged messages, wherein the scheduling information is determined by manipulating at least one of an order of the check nodes and an order of the variable nodes in an LDPC bipartite graph.

Abstract translation: 低密度奇偶校验（LDPC）解码方法包括基于表示在校验节点和可变节点之间交换消息的顺序的调度信息进行LDPC解码的校验节点和可变节点之间的消息交换，并且基于LDPC解码 在所交换的消息上，其中通过在LDPC二分图中操纵校验节点的顺序和可变节点的顺序中的至少一个来确定调度信息。

公开(公告)号：US20160306547A1

公开(公告)日：2016-10-20

申请号：US14686391

申请日：2015-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Amitai PERLSTEIN ,  Amir BENNATAN ,  Hanan LECHTMAN ,  Jun Jin KONG ,  Michael ERLIHSON

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688

Abstract: A memory device controller includes a main processor and a sequencer. The sequencer is configured to: estimate a time interval required to complete execution of a set of atom commands allocated to a channel of a non-volatile memory; calculate, for each of the plurality of atom commands, an urgency value associated with completing execution of a corresponding memory command after expiration of the time interval required to complete execution of the set of atom commands allocated to the channel; schedule each of the plurality of atom commands in the set of atom commands for execution by the non-volatile memory based on the calculated urgency values; and output the plurality of atom commands to the non-volatile memory for execution in the scheduled order.

Abstract translation: 存储器件控制器包括主处理器和定序器。 定序器被配置为：估计完成执行分配给非易失性存储器的通道的一组原子命令所需的时间间隔; 对于所述多个原子命令中的每一个计算与完成执行分配给所述通道的所述原子命令集合所需的时间间隔期满之后完成对应的存储器命令的执行相关联的紧急度值; 基于所计算出的紧急度，安排所述原子命令集中的所述多个原子命令中的每一个，以由所述非易失性存储器执行; 并将多个原子命令输出到非易失性存储器，以按预定顺序执行。