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    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20220122685A1

    公开(公告)日：2022-04-21

    申请号：US17313236

    申请日：2021-05-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunggi AHN ,  Yesin RYU ,  Jun Jin KONG ,  Eunae LEE ,  Jihyun CHOI

    IPC: G11C29/42 ,  G11C29/46 ,  G11C29/14 ,  G11C29/52

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit and a control logic circuit to control the ECC circuit. The memory cell array includes memory cells and a normal cell region and a parity cell region The ECC circuit, in a normal mode, receives a main data, performs an ECC encoding on the main data to generate a parity data and stores the main data and the parity data in the normal cell region and the parity cell region. The ECC circuit, in a test mode, receives a test data including at least one error bit, stores the test data in one of the normal cell region and the parity cell region and performs an ECC decoding on the test data and one of the main data and the parity data to provide a decoding result data to an external device.

    NONVOLATILE MEMORY DEVICES AND METHODS OF CONTROLLING THE SAME
    4.
    发明申请
    NONVOLATILE MEMORY DEVICES AND METHODS OF CONTROLLING THE SAME 有权
    非易失性存储器件及其控制方法

    公开(公告)号：US20160117256A1

    公开(公告)日：2016-04-28

    申请号：US14523159

    申请日：2014-10-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Avner DOR ,  Elona EREZ ,  Shay LANDIS ,  Jun Jin KONG

    IPC: G06F12/10

    CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7203

    Abstract: At least one example embodiment discloses a method of controlling a nonvolatile memory device including a plurality of blocks, each block including a plurality of physical pages. The method includes receiving a plurality of logical pages associated with a first plurality of logical addresses, respectively, and writing the first plurality of logical pages to the plurality physical addresses according to an ascending order of the logical addresses of the first plurality of logical pages.

    Abstract translation: 至少一个示例性实施例公开了一种控制包括多个块的非易失性存储器件的方法，每个块包括多个物理页。 该方法包括分别接收与第一多个逻辑地址相关联的多个逻辑页面，并根据第一多个逻辑页面的逻辑地址的升序将多个逻辑页面写入多个物理地址。

    JOINT SOURCE-CHANNEL ENCODING AND DECODING FOR COMPRESSED AND UNCOMPRESSED DATA
    5.
    发明申请
    JOINT SOURCE-CHANNEL ENCODING AND DECODING FOR COMPRESSED AND UNCOMPRESSED DATA 有权
    压缩和不经过数据的联合源通道编码和解码

    公开(公告)号：US20150280751A1

    公开(公告)日：2015-10-01

    申请号：US14224572

    申请日：2014-03-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Iddo NAISS ,  Uri BEITLER ,  Jun Jin KONG

    IPC: H03M13/00 ,  H03M13/11 ,  G06F11/10

    CPC classification number: H03M13/6312 ,  G06F11/1004 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/152

    Abstract: A memory controller includes a joint source-channel encoder circuit and a joint source-channel decoder circuit. The joint source-channel encoder circuit source encodes received data independent of whether the received data is compressible data, performs error correction coding on the source encoded data, and stores the source encoded data in a memory device. The joint source-channel decoder circuit performs source decoding of the data read from the memory device between iterations of error correction coding of the read data, and outputs the read data to at least one of a buffer memory and a storage device interface. The joint source-channel decoder circuit performs the source decoding of the read data independent of whether the read data is compressed data.

    Abstract translation: 存储器控制器包括联合源通道编码器电路和联合源通道解码器电路。 联合源信道编码器电路源对接收到的数据进行编码，独立于接收到的数据是否是可压缩数据，对源编码数据执行纠错编码，并将源编码数据存储在存储器件中。 联合源信道解码器电路在读取数据的纠错编码的迭代之间对从存储器件读取的数据执行源解码，并将读取的数据输出到缓冲存储器和存储设备接口中的至少一个。 联合源信道解码器电路执行读取数据的源解码，与读数据是否为压缩数据无关。

    MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    7.
    发明申请
    MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220180958A1

    公开(公告)日：2022-06-09

    申请号：US17392382

    申请日：2021-08-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-Rae KIM ,  Myung Kyu LEE ,  Ki Jun LEE ,  Jun Jin KONG ,  Yeong Geol SONG ,  Jin-Hoon JANG

    IPC: G11C29/42 ,  G11C29/44 ,  G11C29/14 ,  G11C29/18 ,  G11C29/00

    Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

    METHOD AND APPARATUS FOR PARTIAL PAGE COMPRESSION
    8.
    发明申请
    METHOD AND APPARATUS FOR PARTIAL PAGE COMPRESSION 有权
    部分页面压缩的方法和装置

    公开(公告)号：US20160371028A1

    公开(公告)日：2016-12-22

    申请号：US14743445

    申请日：2015-06-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Amit BERMAN ,  Jun Jin KONG ,  Uri BEITLER

    IPC: G06F3/06

    CPC classification number: G11C11/5642 ,  G06F12/00 ,  G06F12/0246 ,  G06F2212/1024 ,  G06F2212/401 ,  G06F2212/7202 ,  G06F2212/7203 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5641

    Abstract: A memory system includes a memory device, the memory device including, a memory cell array, and a compression encoder, the memory cell array including a first plurality of multi level cells (MLCs), the memory device being configured to, generate a first partial page by performing one or more first sensing operation on the first plurality of MLCs using one or more first reference voltages, output the first partial page, generate a second partial page by performing a second sensing operation on the first plurality of MLCs based on a second reference voltage, the second reference voltage having a different voltage level than the one or more first reference voltages, generate a second compressed partial page by compressing the second partial page using the compression encoder, and output the compressed second partial page.

    Abstract translation: 存储器系统包括存储器件，存储器件包括存储器单元阵列和压缩编码器，所述存储器单元阵列包括第一多个多电平单元（MLC），所述存储器器件被配置为产生第一部分 通过使用一个或多个第一参考电压对所述第一多个MLC执行一个或多个第一感测操作，输出所述第一部分页面，通过基于第二部分页面对所述第一多个MLC执行第二感测操作来生成第二部分页面 参考电压，具有与所述一个或多个第一参考电压不同的电压电平的所述第二参考电压，通过使用所述压缩编码器压缩所述第二部分页面来生成第二压缩部分页面，并输出所述压缩的第二局部页面。

    METHOD AND APPARATUS FOR ENCODING AND DECODING DATA IN MEMORY SYSTEM
    10.
    发明申请
    METHOD AND APPARATUS FOR ENCODING AND DECODING DATA IN MEMORY SYSTEM 有权
    用于在存储器系统中编码和解码数据的方法和装置

    公开(公告)号：US20150149859A1

    公开(公告)日：2015-05-28

    申请号：US14542828

    申请日：2014-11-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Moshe TWITTO ,  Avner DOR ,  Jun Jin KONG ,  Jung Soo CHUNG

    IPC: G06F11/10

    CPC classification number: G06F11/1012 ,  G06F11/108 ,  G06F2211/109 ,  H03M13/036 ,  H03M13/1157 ,  H03M13/118 ,  H03M13/373 ,  H03M13/3746 ,  H03M13/611

    Abstract: Example embodiments disclose methods and apparatuses for encoding and decoding data in a memory system. In an encoding method according to an example embodiment of inventive concepts, a codeword is generated based on a combination of data to be stored and auxiliary data according to stuck cells and an encoding matrix based on information, regarding coordinates of the stuck cells and values of the stuck cells. The generated codeword includes data corresponding to the values of the stuck cells at addresses corresponding to the coordinates of the stuck cells, in a decoding method according to an example embodiment of inventive concepts, data may be generated by multiplying an inverse matrix of the encoding matrix used for encoding by the codeword.

    Abstract translation: 示例性实施例公开了用于在存储器系统中对数据进行编码和解码的方法和装置。 在根据本发明构思的示例性实施例的编码方法中，基于所存储的数据和辅助数据的组合，根据被卡住的小区和基于关于被卡小区的坐标的信息的编码矩阵来生成码字， 卡住的细胞。 在根据本发明构思的示例性实施例的解码方法中，生成的码字包括对应于与被卡住的小区的坐标对应的地址处的卡住的小区的值的数据，可以通过将编码矩阵的逆矩阵相乘来生成数据 用于编码码字。

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