公开(公告)号：US20230328977A1

公开(公告)日：2023-10-12

申请号：US17883842

申请日：2022-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ansoo PARK ,  Ahreum KIM

IPC: H01L27/11524 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/08

CPC classification number: H01L27/11524 ,  H01L27/0802 ,  H01L27/11529 ,  H01L27/11519

Abstract: An active resistor array of a semiconductor memory device comprises a first active resistor in a first active resistor region; a second active resistor in the first active resistor region and arranged in parallel with the first active resistor, and an isolation element layer interposed therebetween; a third active resistor formed in a second active resistor region; a first selection transistor formed in a first selection transistor region and connected to the second active resistor; and a second selection transistor formed in a second selection transistor region and connected to the third active resistor. The first and second selection transistors are connected to the same gate layer. The gate layer of the first and second selection transistors is on the isolation element layer. Since example embodiments may help to ensure the uniformity of the layout pattern, active resistance distribution may be improved due to reduction in process variation.

公开(公告)号：US20220392532A1

公开(公告)日：2022-12-08

申请号：US17578840

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ansoo PARK ,  Ahreum KIM ,  Homoon SHIN

IPC: G11C16/08 ,  G11C16/30

Abstract: A semiconductor device includes: a peripheral circuit region including circuit elements on a substrate, the circuit elements of a page buffer and a row decoder; and a cell region including gate electrode layers, stacked in a first direction, perpendicular to an upper surface of the substrate, and connected to the row decoder, and channel structures extending in the first direction to penetrate through the gate electrode layers and to be connected to the page buffer. The row decoder includes high-voltage elements, operating at a first power supply voltage, and low-voltage elements operating at a second power supply voltage, lower than the first power supply voltage. Among the high-voltage elements, at least one first high-voltage device is in a first well region doped with impurities having a first conductivity-type. At least one of the low-voltage elements is in a second well region surrounding the first well region and doped with impurities having a second conductivity-type, different from the first conductivity-type.