公开(公告)号：US20160004570A1

公开(公告)日：2016-01-07

申请号：US14789062

申请日：2015-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehan KOH ,  Anuradha OBEROI ,  GopalaKrishna Puligedda SHARMA ,  Raghavan VELAPPAN ,  Priyank Popatlal FALDU

IPC: G06F9/50

CPC classification number: G06F9/5044 ,  G06F9/4843 ,  Y02D10/22 ,  Y02D10/24

Abstract: A parallelization method includes: obtaining profiling information for each job step of a job by performing profiling of the job to be executed on an electronic device; determining at least one job step to be parallelized on a central processing unit (CPU) and at least one heterogeneous unit of the electronic device among a plurality of job steps of the job based on the profiling information; determining a unit to process each unit data among the CPU and the heterogeneous unit based on the profiling information, with respect to the determined at least one job step; and determining a unit to process each task among the CPU and the heterogeneous unit based on the profiling information, with respect to at least one job step including a plurality of separately executable tasks in the determined at least one job step.

Abstract translation: 并行化方法包括：通过对要在电子设备上执行的作业进行轮廓分析来获得作业的每个作业步骤的轮廓信息; 基于所述分析信息，确定在所述作业的多个作业步骤中的中央处理单元（CPU）和所述电子设备的至少一个异构单元之间并行化至少一个作业步骤; 相对于所确定的至少一个作业步骤，确定基于所述轮廓信息处理所述CPU和所述异质单元之间的每个单位数据的单元; 以及基于所述分析信息，确定用于处理所述CPU和所述异构单元中的每个任务的单元，所述至少一个作业步骤包括所确定的至少一个作业步骤中的多个可单独执行的任务。