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公开(公告)号：US11177320B2
公开(公告)日：2021-11-16
申请号：US16561675
申请日：2019-09-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Byeongju Bae , Duckhee Lee
IPC: H01L27/24 , H01L23/528 , H01L45/00
Abstract: Disclosed are variable resistance memory devices and methods of fabricating the same. The variable resistance memory device may include: a plurality of memory cells, each comprising a variable resistance pattern and a switching pattern; a plurality of conductive lines to which the memory cell is connected; a bottom electrode connecting at least one of the conductive lines to the variable resistance pattern; and a spacer pattern formed on the bottom electrode to be in contact with the variable resistance pattern. The spacer pattern includes a dielectric material doped with an impurity.
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公开(公告)号：US11930646B2
公开(公告)日：2024-03-12
申请号：US17224303
申请日：2021-04-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeonghee Park , Jonguk Kim , Byeongju Bae
CPC classification number: H10B63/80 , H10B63/24 , H10N70/063 , H10N70/231
Abstract: A resistive memory device includes a plurality of first conductive lines in a first area and a second area on a substrate, a plurality of second conductive lines in the first area and the second area, the plurality of second conductive lines being apart from the plurality of first conductive lines in a vertical direction, and a plurality of memory cells connected to the first and second conductive lines at a plurality of intersections between the plurality of first and second conductive lines in the first area and the second area. The plurality of memory cells include an active memory cell in the first area and a dummy memory cell in the second area. The active memory cell including a first resistive memory pattern having a first width and the dummy memory cell including a second resistive memory pattern having a second width greater than the first width.
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公开(公告)号：US20220037401A1
公开(公告)日：2022-02-03
申请号：US17224303
申请日：2021-04-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeonghee Park , Jonguk Kim , Byeongju Bae
Abstract: A resistive memory device includes a plurality of first conductive lines in a first area and a second area on a substrate, a plurality of second conductive lines in the first area and the second area, the plurality of second conductive lines being apart from the plurality of first conductive lines in a vertical direction, and a plurality of memory cells connected to the first and second conductive lines at a plurality of intersections between the plurality of first and second conductive lines in the first area and the second area. The plurality of memory cells include an active memory cell in the first area and a dummy memory cell in the second area. The active memory cell including a first resistive memory pattern having a first width and the dummy memory cell including a second resistive memory pattern having a second width greater than the first width.
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