公开(公告)号：US12127489B2

公开(公告)日：2024-10-22

申请号：US18170947

申请日：2023-02-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Han-Ting Tsai ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC分类号： H10B63/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10N70/884 ,  H10B61/22 ,  H10B63/30 ,  H10B63/82 ,  H10B63/84 ,  H10N50/01 ,  H10N50/80 ,  H10N70/023 ,  H10N70/063 ,  H10N70/24 ,  H10N70/245 ,  H10N70/826 ,  H10N70/8416 ,  H10N70/8833

摘要： An IC structure comprises a substrate, a first dielectric structure, a second dielectric structure, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first dielectric structure is over the memory region. The second dielectric structure laterally extends from the first dielectric structure to over the logic region. The second dielectric structure has a thickness less than a thickness of the first dielectric structure. The first via structure extends through the first dielectric structure. A top segment of the first via structure is higher than a top surface of the first dielectric structure. The first memory cell structure is over the first via structure.

公开(公告)号：US12127485B2

公开(公告)日：2024-10-22

申请号：US17421418

申请日：2020-01-07

申请人： NANOBRIDGE SEMICONDUCTOR, INC.

发明人： Naoki Banno ,  Munehiro Tada ,  Hideaki Numata ,  Koichiro Okamoto

IPC分类号： H01L27/24 ,  H10B63/00 ,  H10N70/00

CPC分类号： H10N70/023 ,  H10B63/30 ,  H10N70/063 ,  H10N70/8416 ,  H10N70/883

摘要： A switching element that has reduced switching voltage and leakage current and that demonstrates high reliability and low power consumption is achieved as a result of comprising: a first insulation layer in which first wiring mainly consisting of copper is embedded in a first wiring groove that opens upward; a second insulation layer which is formed on an upper surface of the first insulation layer and the first wiring and has an opening that reaches the first insulation layer and the first wiring; a first electrode which is the portion of the first wiring that is exposed from the opening; an oxygen supply layer which is formed on an upper surface of the second insulation layer, generates oxygen plasma during etching to form the opening in the second insulation layer, and remains at least in the vicinity of the opening of the upper surface of the second insulation layer; an ion conducting layer which is formed on the upper surface of the first insulation layer and the first electrode that are exposed from the opening, an inner surface of the opening of the second insulation layer, and an upper surface of the oxygen supply layer; and a second electrode that is formed on an upper surface of the ion conducting layer.

公开(公告)号：US20240334847A1

公开(公告)日：2024-10-03

申请号：US18738161

申请日：2024-06-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chieh Huang ,  Jieh-Jang Chen ,  Feng-Jia Shiu ,  Chern-Yow Hsu

IPC分类号： H10N70/00 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/768 ,  H10B63/00 ,  H10N70/20

CPC分类号： H10N70/8418 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76879 ,  H10B63/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8413 ,  H10N70/8828 ,  H10N70/8833

摘要： A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

公开(公告)号：US20240324474A1

公开(公告)日：2024-09-26

申请号：US18735715

申请日：2024-06-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Der CHIH ,  Wen-Zhang LIN ,  Yun-Sheng CHEN ,  Jonathan Tsung-Yung CHANG ,  Chrong-Jung LIN ,  Ya-Chin KING ,  Cheng-Jun LIN ,  Wang-Yi LEE

IPC分类号： H10N70/00 ,  H10B63/00

CPC分类号： H10N70/021 ,  H10B63/80 ,  H10N70/063 ,  H10N70/066 ,  H10N70/068 ,  H10N70/841

摘要： A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

公开(公告)号：US20240298555A1

公开(公告)日：2024-09-05

申请号：US18177397

申请日：2023-03-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sheng-Siang Ruan ,  Chia-Wen Zhong ,  Tzu-Yu Lin ,  Yao-Wen Chang ,  Ching Ju Yang ,  Chin I Wang

IPC分类号： H10N70/00 ,  H10N70/20

CPC分类号： H10N70/8416 ,  H10N70/023 ,  H10N70/026 ,  H10N70/063 ,  H10N70/245 ,  H10N70/883 ,  H01J37/32091 ,  H01J2237/3321

摘要： A semiconductor device that includes a semiconductor substrate, a bottom electrode over the semiconductor substrate, a switching layer over the bottom electrode, a metal ion source layer over the switching layer, and a top electrode over the metal ion source layer. The switching layer includes a compound having aluminum, oxygen, and nitrogen.

公开(公告)号：US20240276894A1

公开(公告)日：2024-08-15

申请号：US18646334

申请日：2024-04-25

申请人： STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

发明人： Philippe BOIVIN ,  Roberto SIMOLA ,  Yohann MOUSTAPHA-RABAULT

IPC分类号： H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC分类号： H10N70/231 ,  H10B63/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/066 ,  H10N70/068 ,  H10N70/882 ,  H10N70/883

摘要： The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.

公开(公告)号：US20240276891A1

公开(公告)日：2024-08-15

申请号：US18343443

申请日：2023-06-28

申请人： SK hynix Inc.

发明人： Woo Tae LEE ,  Su Jee KIM

IPC分类号： H10N70/00 ,  H10B63/00

CPC分类号： H10N70/066 ,  H10B63/84 ,  H10N70/063 ,  H10N70/8613 ,  H10N70/883

摘要： A semiconductor device may include first conductive lines extending in a first direction; second conductive lines extending in a second direction that intersects the first direction; memory cells disposed between the first conductive lines and the second conductive lines in a third direction perpendicular to each of the first and the second directions, each of the memory cells comprising a variable resistance pattern; first gap-fill patterns disposed between the memory cells and having first thermal conductivity; and second gap-fill patterns disposed on the first gap-fill patterns in the third direction and having second thermal conductivity lower than the first thermal conductivity, wherein an interface between each of the second gap-fill patterns and each a corresponding one of the first gap-fill patterns is disposed between an upper surface and a lower surface of the variable resistance pattern.

公开(公告)号：US12063794B2

公开(公告)日：2024-08-13

申请号：US17334810

申请日：2021-05-31

申请人： Southern University of Sciene and Technology

发明人： Guobiao Zhang

IPC分类号： H10B63/00 ,  H10N70/00

CPC分类号： H10B63/84 ,  H10B63/20 ,  H10N70/841 ,  H10N70/063

摘要： High-density three-dimensional (3-D) vertical memory (3D-MV) includes lightly-doped-segment (LDS) 3D-MV and non-circular-hole (NCH) 3D-MV. The preferred LDS 3D-MV takes advantage of longitudinal space, instead of lateral space, to guarantee normal write operation. On the other hand, the lateral cross-section of the memory hole of the preferred NCH 3D-MV includes at least two intersecting pairs of parallel sides, with each pair formed through a single DUV exposure and having a minimum spacing

公开(公告)号：US12041860B2

公开(公告)日：2024-07-16

申请号：US17581153

申请日：2022-01-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Der Chih ,  Wen-Zhang Lin ,  Yun-Sheng Chen ,  Jonathan Tsung-Yung Chang ,  Chrong-Jung Lin ,  Ya-Chin King ,  Cheng-Jun Lin ,  Wang-Yi Lee

IPC分类号： H10N70/00 ,  H10B63/00

CPC分类号： H10N70/021 ,  H10B63/80 ,  H10N70/063 ,  H10N70/066 ,  H10N70/068 ,  H10N70/841

摘要： A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

公开(公告)号：US20240237359A1

公开(公告)日：2024-07-11

申请号：US18152072

申请日：2023-01-09

申请人： TetraMem Inc.

发明人： Ning Ge ,  Minxian Zhang ,  Mingche Wu ,  Gary Miner

IPC分类号： H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10B63/84 ,  H10B63/30 ,  H10N70/063 ,  H10N70/253 ,  H10N70/841 ,  H10N70/8833

摘要： An apparatus including a plurality of resistive random-access memory (RRAM) devices is provided. The RRAM devices are fabricated on a single substrate in some embodiments. The apparatus includes an interconnect layer fabricated on the substrate. A first RRAM device of the RRAM devices includes a first bottom electrode, a first top electrode; and a first filament-forming layer fabricated between the first bottom electrode and the first top electrode. A second RRAM device of the RRAM devices includes a second bottom electrode, a second top electrode, and a second filament-forming layer fabricated between the second bottom electrode and the second top electrode. The first bottom electrode and the second bottom electrode are fabricated on multiple metallic pads or metallic vias of the interconnect layer. The first filament-forming layer and the second filament-forming layer include different switching oxides.