公开(公告)号：US10804403B2

公开(公告)日：2020-10-13

申请号：US16437056

申请日：2019-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daewon Ha ,  Seungseok Ha ,  Byoung Hak Hong

IPC: H01L29/78 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin.

公开(公告)号：US10361310B2

公开(公告)日：2019-07-23

申请号：US15463187

申请日：2017-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daewon Ha ,  Seungseok Ha ,  Byoung Hak Hong

IPC: H01L29/41 ,  H01L29/78 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin.

公开(公告)号：US09773785B2

公开(公告)日：2017-09-26

申请号：US15219374

申请日：2016-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyu Baik Chang ,  Byoung Hak Hong ,  Yoon Suk Kim ,  Seung Hyun Song

IPC: H01L27/088 ,  H01L29/06 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/0924 ,  H01L29/7843 ,  H01L29/7845

Abstract: A semiconductor device includes first and second fins on first and second regions of a substrate, a first trench overlapping a vertical end portion of the first fin and including first upper and lower portions, the first upper and lower portions separated by an upper surface of the first fin, a second trench overlapping a vertical end portion of the second fin and including second upper and lower portions separated by an upper surface of the second fin, a first dummy gate electrode including first metal oxide and filling layers, the first metal oxide layer filling the first lower portion of the first trench and is along a sidewall of the first upper portion of the first trench, and a second dummy gate electrode filling the second trench and including second metal oxide and filling layers, the second metal oxide layer extending along sidewalls of the second trench.