公开(公告)号：US20240064996A1

公开(公告)日：2024-02-22

申请号：US18170136

申请日：2023-02-16

申请人： Samsung Electronics Co., Ltd.

发明人： Kiheun Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Ilho Myeong ,  Daewon Ha

IPC分类号： H10B51/20 ,  H10B51/10 ,  H01L23/528 ,  H01L29/51 ,  H01L29/78

CPC分类号： H10B51/20 ,  H10B51/10 ,  H01L23/5283 ,  H01L29/516 ,  H01L29/78391

摘要： A semiconductor device includes first and second cell arrays. The first cell array includes a first gate electrode that extends in a vertical direction, a first channel pattern on a side surface of the first gate electrode, and a first bit line electrically connected to the first channel pattern. The second cell array includes a second gate electrode that extends in the vertical direction, a second channel pattern on a side surface of the second gate electrode, and a second bit line electrically connected to the second channel pattern. A first bit line pad is electrically connected to the first bit line and a second bit line pad is electrically connected to the second bit line. The first bit line pad is spaced apart from the second bit line pad with the first and second cell arrays therebetween.

公开(公告)号：US20230402460A1

公开(公告)日：2023-12-14

申请号：US18239241

申请日：2023-08-29

申请人： Samsung Electronics Co., Ltd.

发明人： SUNGMIN KIM ,  Daewon Ha

IPC分类号： H01L27/092 ,  H01L29/08 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L23/522

CPC分类号： H01L27/0924 ,  H01L29/0847 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42356 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823814 ,  H01L23/5226 ,  H01L21/02636

摘要： A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.

公开(公告)号：US09276087B2

公开(公告)日：2016-03-01

申请号：US14262937

申请日：2014-04-28

申请人： Samsung Electronics Co., Ltd.

发明人： Sungmin Kim ,  Sung-Dae Suk ,  Jaehoo Park ,  Dongho Cha ,  Daewon Ha

IPC分类号： H01L21/84 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/66795 ,  H01L21/02233 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

摘要： A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.

摘要翻译： 制造半导体器件的方法包括：图案化衬底以形成有源鳍片，形成与衬底上的有源鳍片交叉的牺牲栅极图案，在牺牲栅极图案上形成层间绝缘层，去除牺牲栅极图案以形成 间隙区域使层间绝缘层中的活性鳍片曝光，并且氧化由间隙区域暴露的活性鳍片的一部分，以在活性鳍片和衬底之间形成绝缘图案。

公开(公告)号：US09130040B2

公开(公告)日：2015-09-08

申请号：US14248594

申请日：2014-04-09

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： JaeHoo Park ,  Daewon Ha ,  Uihui Kwon ,  Sung-Dae Suk

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/092

CPC分类号： H01L29/785 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/7853

摘要： Provided are a semiconductor device and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an active fin on a substrate; oxidizing a portion of the active fin to form an insulating pattern between the active fin and the substrate; forming a first gate pattern on the substrate, wherein the first gate pattern crosses the active fin; exposing the substrate on both sides of the first gate pattern; and forming source/drain regions on the exposed substrate.

摘要翻译： 提供半导体器件及其制造方法。 制造半导体器件的方法包括：在衬底上形成有源散热片; 氧化活性鳍片的一部分以在活性鳍片和衬底之间形成绝缘图案; 在所述衬底上形成第一栅极图案，其中所述第一栅极图案与所述有源鳍片交叉; 在第一栅极图案的两侧上暴露衬底; 以及在暴露的衬底上形成源极/漏极区域。

公开(公告)号：US11798949B2

公开(公告)日：2023-10-24

申请号：US17712571

申请日：2022-04-04

申请人： Samsung Electronics Co., Ltd.

发明人： Munhyeon Kim ,  Soonmoon Jung ,  Daewon Ha

IPC分类号： H01L27/12 ,  H01L29/08 ,  H01L21/84 ,  H01L29/423 ,  H01L29/10

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42368

摘要： A multi-channel semiconductor-on-insulator (SOI) transistor includes a substrate having an electrically insulating layer thereon and a semiconductor active layer on the electrically insulating layer. A vertical stack of spaced-apart insulated gate electrodes, which are buried within the semiconductor active layer, is also provided. This vertical stack includes a first insulated gate electrode extending adjacent the electrically insulating layer and an (N−1)th insulated gate electrode that is spaced from a surface of the semiconductor active layer, where N is a positive integer greater than two. An Nth insulated gate electrode is provided on the surface of the semiconductor active layer. A pair of source/drain regions are provided within the semiconductor active layer. These source/drain regions extend adjacent opposing sides of the vertical stack of spaced-apart insulated gate electrodes. In some of these aspects, the semiconductor active layer extends between the pair of source/drain regions and the electrically insulating layer, whereas the first insulated gate electrode contacts the electrically insulating layer.

公开(公告)号：US11798947B2

公开(公告)日：2023-10-24

申请号：US17675163

申请日：2022-02-18

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sungmin Kim ,  Daewon Ha

IPC分类号： H01L27/092 ,  H01L29/08 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L23/522 ,  H01L21/02

CPC分类号： H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42356 ,  H01L21/02636 ,  H01L21/823878

摘要： A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.

公开(公告)号：US20230309317A1

公开(公告)日：2023-09-28

申请号：US18059010

申请日：2022-11-28

申请人： Samsung Electronics Co., Ltd.

发明人： Hyuncheol KIM ,  Yongseok Kim ,  Kiheun Lee ,  Sangkil Lee ,  Daewon Ha

IPC分类号： H10B53/20 ,  H10B53/10 ,  H01L23/528

CPC分类号： H01L27/11514 ,  H01L27/11504 ,  H01L23/5283

摘要： A semiconductor memory device is provided. The semiconductor memory device may include a semiconductor substrate; a data storage layer including capacitors disposed on the semiconductor substrate; a switching element layer on the data storage layer and including transistors connected to the respective capacitors; and a wiring layer on the switching element layer and including bit lines connected to the transistors, The respective transistors include an active pattern, a word line that crosses the active pattern such that the word line surrounds a first sidewall, a second sidewall and a top surface of the active pattern, and a ferroelectric layer between the word line and the active patter.

公开(公告)号：US20230086084A1

公开(公告)日：2023-03-23

申请号：US17554483

申请日：2021-12-17

申请人： Samsung Electronics Co., Ltd.

发明人： Seungchan Yun ,  Inchan Hwang ,  Gunho Jo ,  Jeonghyuk Yim ,  Byounghak Hong ,  Kang-ill Seo ,  Ming He ,  JaeHyun Park ,  Mehdi Saremi ,  Rebecca Park ,  Harsono Simka ,  Daewon Ha

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234

摘要： Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

公开(公告)号：US20190206867A1

公开(公告)日：2019-07-04

申请号：US16030224

申请日：2018-07-09

申请人： Samsung Electronics Co., Ltd.

发明人： Jung Han LEE ,  Sungchul Park ,  Yunil Lee ,  Byoung-gi Kim ,  Yeongmin Jeon ,  Daewon Ha ,  Inchan Hwang ,  Jae Hyun Park ,  Woocheol Shin

IPC分类号： H01L27/092 ,  H01L29/423 ,  H01L27/02 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/306 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L27/0924 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor substrate includes a plurality of gate electrodes crossing active patterns on a substrate and extending in a second direction, the gate electrodes spaced apart in the second direction from each other, a gate separation pattern having a major axis in the first direction and between two of the gate electrodes, the two of the gate electrodes adjacent to each other in the second direction, and a plurality of gate spacers covering sidewalls of respective ones of the gate electrodes, the gate spacers crossing the gate separation pattern and extending in the second direction. The gate separation pattern includes a lower portion extending in the first direction, an intermediate portion protruding from the lower portion and having a first width, and an upper portion between two adjacent gate spacers and protruding from the intermediate portion, the upper portion having a second width less than the first width.

公开(公告)号：US09208875B2

公开(公告)日：2015-12-08

申请号：US14162991

申请日：2014-01-24

申请人： Samsung Electronics Co., Ltd.

发明人： Kwang-Woo Lee ,  Daewon Ha

IPC分类号： G11C13/00 ,  G11C11/56

CPC分类号： G11C13/0069 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0064

摘要： A writing method of a nonvolatile memory device is provided which receiving data, a target time, and a target resistance value; writing the data at a memory cell; calculating a resistance drift coefficient based on resistance values of the memory cell read on at least two times; calculating a resistance value of the memory cell on the target time using the resistance drift coefficient; and determining whether the resistance value calculated satisfies the target resistance value.

摘要翻译： 提供了一种非易失性存储器件的写入方法，其接收数据，目标时间和目标电阻值; 将数据写入存储单元; 基于读取的存储器单元的电阻值计算电阻漂移系数至少两次; 使用电阻漂移系数计算目标时间上的存储单元的电阻值; 以及确定所计算的电阻值是否满足目标电阻值。