公开(公告)号：US20220020766A1

公开(公告)日：2022-01-20

申请号：US17211129

申请日：2021-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Chul JANG ,  Sang-Yong PARK ,  Jae Duk LEE

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11565

Abstract: A semiconductor memory device includes a stacked structure on a substrate and a vertical structure penetrating the stacked structure. The stacked structured includes a plurality of conductive lines stacked on the substrate. The vertical structure may include a vertical insulating pattern and a channel film extending along sidewalls of the vertical insulating pattern. The vertical insulating pattern may include an inner region and an outer region. The outer region of the vertical insulating pattern may be placed between the channel film and the inner region of the vertical insulating pattern, and the outer region of the vertical insulating pattern may include a diffused metal.

公开(公告)号：US20250120082A1

公开(公告)日：2025-04-10

申请号：US18983846

申请日：2024-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Chul JANG ,  Sang-Yong PARK ,  Jae Duk LEE

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor memory device includes a stacked structure on a substrate and a vertical structure penetrating the stacked structure. The stacked structured includes a plurality of conductive lines stacked on the substrate. The vertical structure may include a vertical insulating pattern and a channel film extending along sidewalls of the vertical insulating pattern. The vertical insulating pattern may include an inner region and an outer region. The outer region of the vertical insulating pattern may be placed between the channel film and the inner region of the vertical insulating pattern, and the outer region of the vertical insulating pattern may include a diffused metal.