公开(公告)号：US20220271057A1

公开(公告)日：2022-08-25

申请号：US17666448

申请日：2022-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yong PARK ,  Jin-Hong PARK ,  Sungjoo LEE

IPC: H01L27/11597 ,  H01L29/51 ,  H01L29/78

Abstract: A semiconductor memory device capable of improving performance by the use of a charge storage layer including a ferroelectric material is provided. The semiconductor memory device includes a substrate, a tunnel insulating layer contacting the substrate, on the substrate, a charge storage layer contacting the tunnel insulating layer and including a ferroelectric material, on the tunnel insulating layer, a barrier insulating layer contacting the charge storage layer, on the charge storage layer, and a gate electrode contacting the barrier insulating layer, on the barrier insulating layer.

公开(公告)号：US20220246642A1

公开(公告)日：2022-08-04

申请号：US17726637

申请日：2022-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yong PARK ,  Jintaek PARK

IPC: H01L27/11582 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/28 ,  H01L27/02 ,  H01L27/11565 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11578 ,  H01L23/528 ,  H01L27/1157

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

公开(公告)号：US20180004541A1

公开(公告)日：2018-01-04

申请号：US15394518

申请日：2016-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeok JANG ,  Yae Seul LEE ,  Sang-Yong PARK ,  Tae Sun YOU ,  Seong Wook HWANG

IPC: G06F9/44 ,  G06F13/40 ,  G06F13/24 ,  G06F13/42 ,  G06F1/32

CPC classification number: G06F9/4418 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F13/24 ,  G06F13/4022 ,  G06F13/4291 ,  Y02D10/126 ,  Y02D10/151

Abstract: An integrated circuit device is provided. The integrated circuit device may include a central processing unit (CPU) configured to operate in one of a plurality of modes and a wake-up control circuit configured to control the CPU. The wake-up control circuit may include a clock generator configured to generate an internal clock signal, a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and a controller configured to control the CPU and the clock generator based on the external signal.

公开(公告)号：US20140048873A1

公开(公告)日：2014-02-20

申请号：US14057094

申请日：2013-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Joo SHIM ,  Han-Soo KIM ,  Won-Seok CHO ,  Jae-Hoon JANG ,  Sang-Yong PARK

IPC: H01L29/78

CPC classification number: H01L29/7831 ,  H01L27/11582 ,  H01L29/7926

Abstract: A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.

Abstract translation: 半导体器件包括衬底上的半导体图案，半导体图案的侧壁上的栅极结构，栅极结构彼此间隔开，栅极结构之间的绝缘夹层，其中最上层的绝缘中间层低于栅极结构的上表面 半导体图案，与基板接触并突出在最上层绝缘夹层之上的公共源极线，在半导体图案上的公共源极线上的共同源极线上的蚀刻停止层图案，其中共同源极线突出在最上面的绝缘中间层之上，在 最上层的绝缘中间层和延伸穿过附加绝缘夹层的接触插塞分别与半导体图案和公共源极线接触。

公开(公告)号：US20240088239A1

公开(公告)日：2024-03-14

申请号：US18199516

申请日：2023-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yong PARK ,  Jin-Hong Park ,  Ju-Hee Lee

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate. A first channel pattern is disposed on the substrate. The first channel pattern includes a first side and a second side opposite to each other in a first direction. A first gate electrode is disposed on the first side of the first channel pattern. A first source/drain electrode is disposed on the first side of the first channel pattern. A second source/drain electrode is disposed on the second side of the first channel pattern. The first gate electrode overlaps the second source/drain electrode in the first direction.

公开(公告)号：US20140108835A1

公开(公告)日：2014-04-17

申请号：US14050793

申请日：2013-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yong PARK ,  Jekook KIM ,  Chan-Woo PARK ,  Younghoon LEE

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/26 ,  G06F9/4401

Abstract: A power management integrated circuit includes a nonvolatile memory configured to store code data for driving the power management integrated circuit; a processor configured to execute program data stored at a volatile memory; and a decompression logic separated from the processor, the decompression logic being formed of hardware, configured to decompress the code data to generate program data, and configured to store the program data at the volatile memory.

Abstract translation: 电源管理集成电路包括非易失性存储器，被配置为存储用于驱动电源管理集成电路的代码数据; 处理器，被配置为执行存储在易失性存储器的程序数据; 以及与处理器分离的解压缩逻辑，所述解压缩逻辑由硬件形成，被配置为解压缩所述代码数据以生成程序数据，并且被配置为将所述程序数据存储在所述易失性存储器。

公开(公告)号：US20240172444A1

公开(公告)日：2024-05-23

申请号：US18430189

申请日：2024-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yong PARK ,  Jintaek PARK

IPC: H10B43/27 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/528 ,  H01L27/02 ,  H01L29/66 ,  H01L29/792 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/31144 ,  H01L21/32139 ,  H01L23/5283 ,  H01L27/0207 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/7926 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35 ,  H01L2924/0002

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

公开(公告)号：US20230245887A1

公开(公告)日：2023-08-03

申请号：US18093653

申请日：2023-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yong PARK ,  Jin-Hyuk KIM ,  Jin-Hong PARK ,  Sejin KYUNG

IPC: H01L21/02 ,  H01L27/146 ,  H01L29/24 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/02614 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02568 ,  H01L27/14616 ,  H01L27/1461 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/0673

Abstract: Disclosed are methods of forming PN junction structures, methods of fabricating semiconductor devices using the same, and semiconductor devices fabricated by the same. The method of forming a PN junction structure includes: forming on a substrate a first material layer that includes first transition metal atoms and first chalcogen atoms, loading the first material layer into a process chamber and supplying a gas of second chalcogen atoms, and forming a second material layer by substituting the second chalcogen atoms for the first chalcogen atoms on a selected portion of the first material layer. The first material layer has one of n-type conductivity and p-type conductivity. The second material layer has the other of the n-type conductivity and the p-type conductivity.

公开(公告)号：US20220020766A1

公开(公告)日：2022-01-20

申请号：US17211129

申请日：2021-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Chul JANG ,  Sang-Yong PARK ,  Jae Duk LEE

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11565

Abstract: A semiconductor memory device includes a stacked structure on a substrate and a vertical structure penetrating the stacked structure. The stacked structured includes a plurality of conductive lines stacked on the substrate. The vertical structure may include a vertical insulating pattern and a channel film extending along sidewalls of the vertical insulating pattern. The vertical insulating pattern may include an inner region and an outer region. The outer region of the vertical insulating pattern may be placed between the channel film and the inner region of the vertical insulating pattern, and the outer region of the vertical insulating pattern may include a diffused metal.

公开(公告)号：US20190220288A1

公开(公告)日：2019-07-18

申请号：US16352185

申请日：2019-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeok Jang ,  Yae Seul LEE ,  Sang-Yong PARK ,  Tae Sun YOU ,  Seong Wook HWANG

IPC: G06F9/4401 ,  G06F13/24 ,  G06F1/3287 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F9/4418 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F13/24 ,  G06F13/4022 ,  G06F13/4291 ,  Y02D10/126 ,  Y02D10/151

Abstract: An integrated circuit device is provided. The integrated circuit device may include a central processing unit (CPU) configured to operate in one of a plurality of modes and a wake-up control circuit configured to control the CPU. The wake-up control circuit may include a clock generator configured to generate an internal clock signal, a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and a controller configured to control the CPU and the clock generator based on the external signal.