公开(公告)号：US20220189991A1

公开(公告)日：2022-06-16

申请号：US17687131

申请日：2022-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungjin LEE ,  Dong-Sik Lee ,  Joon-Sung Lim

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure that includes a plurality of dielectric layers spaced apart from each other on a substrate, a plurality of electrodes interposed between the plurality of dielectric layers, and a plurality of stopper layers interposed between the plurality of dielectric layers; and a vertical channel structure that penetrates the stack structure. Each of the plurality of electrodes and the plurality of stopper layers is disposed in a corresponding empty space interposed between the plurality of dielectric layers, the plurality of stopper layers includes a first stopper layer and a second stopper layer that is interposed between the first stopper layer and the substrate, and at least one of the plurality of electrodes is interposed between the first stopper layer and the second stopper layer.

公开(公告)号：US20210035910A1

公开(公告)日：2021-02-04

申请号：US16875174

申请日：2020-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung KIM ,  Woosung YANG ,  Jungsok LEE ,  Byungjin LEE

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/768

Abstract: A semiconductor memory includes electrode structures that each includes horizontal electrodes stacked on each other a substrate, vertical electrodes between the electrode structures and extending along the horizontal electrodes, first contacts connected to the horizontal electrodes at end portions of the electrode structures, second contacts connected to upper portions of the vertical electrodes, and a first interconnection structure connected to top surfaces of the second contacts. The first interconnection structure includes first and second sub-interconnection lines. The sub-interconnection lines extend in a first direction and contact the top surfaces of the second contacts. The second sub-interconnection lines extended in a second direction crossing the first direction and contact the first sub-interconnection lines.

公开(公告)号：US20210217760A1

公开(公告)日：2021-07-15

申请号：US17021416

申请日：2020-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung YANG ,  Byungjin LEE ,  Bumkyu KANG ,  Dong-Sik LEE

IPC: H01L27/11539 ,  H01L27/11551 ,  H01L27/11543 ,  G11C16/08 ,  H01L27/11578 ,  H01L27/11573 ,  H01L23/522 ,  G11C7/18 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/11519

Abstract: A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.