公开(公告)号：US20210217760A1

公开(公告)日：2021-07-15

申请号：US17021416

申请日：2020-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung YANG ,  Byungjin LEE ,  Bumkyu KANG ,  Dong-Sik LEE

IPC: H01L27/11539 ,  H01L27/11551 ,  H01L27/11543 ,  G11C16/08 ,  H01L27/11578 ,  H01L27/11573 ,  H01L23/522 ,  G11C7/18 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/11519

Abstract: A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

公开(公告)号：US20220149072A1

公开(公告)日：2022-05-12

申请号：US17375273

申请日：2021-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimo GU ,  Bumkyu KANG ,  Sungmin HWANG

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor device includes a substrate, a lower stack structure on the substrate and including lower gate electrodes stacked apart from each other, an upper stack structure on the lower stack structure and including upper gate electrodes stacked apart from each other, a lower channel structure penetrating through the lower stack structure and including a lower channel layer, and a lower channel insulating layer on the lower channel layer the lower channel insulating layer surrounding a lower slit, and an upper channel structure penetrating through the upper stack structure and including an upper channel layer and an upper channel insulating layer on the upper channel layer, the upper channel insulating layer surrounding an upper slit. A width of the lower slit is greater than a width of the upper slit, and a thickness of the lower channel insulating layer is greater than a thickness of the upper channel insulating layer.

公开(公告)号：US20250056806A1

公开(公告)日：2025-02-13

申请号：US18610514

申请日：2024-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Bumkyu KANG ,  Junyong PARK ,  Sukkang SUNG

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device and a data storage system are provided. The semiconductor device includes a peripheral circuit structure; a stack structure vertically overlapping the peripheral circuit structure; and a separation structure penetrating through the stack structure. The stack structure includes a plurality of blocks spaced apart from each other by a first portion of the separation structure, each of the plurality of blocks includes insulating layers and conductive layers alternately stacked in a vertical direction, and the plurality of blocks include first blocks and a plurality of capacitor blocks disposed between first blocks adjacent to each other among the first blocks.

公开(公告)号：US20220384476A1

公开(公告)日：2022-12-01

申请号：US17563547

申请日：2021-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyoung KIM ,  Bumkyu KANG ,  Joonsung LIM ,  Sukkang SUNG

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device includes a substrate having a cell region and a connection region, a first stack structure with a plurality of first gate layers and a plurality of first interlayer insulating layers, and a second stack structure with a plurality of second gate layers and a plurality of second interlayer insulating layers . Each of the first gate layers includes a central portion in the cell region of the substrate and an end portion in the connection region of the substrate. Each of the second gate layers includes a central portion in the cell region of the substrate and an end portion in the connection region of the substrate. A thickness difference between the end and central portions of each first gate layer is different from a thickness difference between the end and central portions of each second gate layer.