公开(公告)号：US20220199126A1

公开(公告)日：2022-06-23

申请号：US17377654

申请日：2021-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sucheol LEE ,  Changkyu SEOL ,  Byungsuk WOO

IPC: G11C5/14 ,  G11C11/4074

Abstract: A receiver including: a data processing circuit, in a training mode, to compare a multi-level signal with first and second voltage signals, and to generate data density signals; a counter circuit to count the data density signals to generate counting values; a control circuit to store, in a register set, a voltage range, counting values corresponding to the voltage range and a control code associated with a first level of the first voltage signal and a second level of the second voltage signal, the voltage range being based on the first and second voltage signals; and a voltage generation circuit, in the training mode, to apply the first and second voltage signals to the data processing circuit and to increase the first level and the second level by a difference between the first and second control signals in response to the control code from the control circuit.

公开(公告)号：US20220188013A1

公开(公告)日：2022-06-16

申请号：US17356687

申请日：2021-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungsuk WOO ,  Changkyu SEOL ,  Sucheol LEE

IPC: G06F3/06

Abstract: A memory device includes: a memory cell array; a data selector configured to receive data from the memory cell array, and to output the received data as first sub-data and second sub-data; a cyclic redundancy check (CRC) generator configured to generate first CRC values corresponding to the first sub-data, and to generate second CRC values corresponding to the second sub-data; a CRC selector configured to determine an order of the first CRC values and the second CRC values, and to output one of the first CRC values and one of the second CRC values according to the determined order; and a transmitter configured to receive the first CRC values and the second CRC values according to the determined order, and to transmit CRC values of the data by a multilevel signaling method.

公开(公告)号：US20220121388A1

公开(公告)日：2022-04-21

申请号：US17394488

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungsuk WOO ,  Younguk CHANG ,  Yongho CHO

IPC: G06F3/06

Abstract: In a method of generating a signal for test in a memory device configured to output a multi-level signal, an operation mode is set to a first test mode. During the first test mode, first data bits included in a plurality of test data are arranged based on a first scheme. Each of the plurality of test data includes two or more data bits. During the first test mode, a first test result signal having two voltage levels is generated based on the first data bits according to the first scheme. The operation mode is set to a second test mode during which second data bits included in the plurality of test data are arranged based on a second scheme. During the second test mode, a second test result signal having the two voltage levels is generated based on the second data bits according to the second scheme.