中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.018 seconds)

    MEMORY DEVICE, DATA OUTPUTING METHOD THEREOF, AND MEMORY SYSTEM HAVING THE SAME
    2.
    发明申请
    MEMORY DEVICE, DATA OUTPUTING METHOD THEREOF, AND MEMORY SYSTEM HAVING THE SAME 有权

    公开(公告)号：US20220188013A1

    公开(公告)日：2022-06-16

    申请号：US17356687

    申请日：2021-06-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byungsuk WOO ,  Changkyu SEOL ,  Sucheol LEE

    IPC: G06F3/06

    Abstract: A memory device includes: a memory cell array; a data selector configured to receive data from the memory cell array, and to output the received data as first sub-data and second sub-data; a cyclic redundancy check (CRC) generator configured to generate first CRC values corresponding to the first sub-data, and to generate second CRC values corresponding to the second sub-data; a CRC selector configured to determine an order of the first CRC values and the second CRC values, and to output one of the first CRC values and one of the second CRC values according to the determined order; and a transmitter configured to receive the first CRC values and the second CRC values according to the determined order, and to transmit CRC values of the data by a multilevel signaling method.

    CIRCUIT CONFIGURED TO COMPENSATE FOR TIMING SKEW AND OPERATION METHOD THEREOF
    3.
    发明申请
    CIRCUIT CONFIGURED TO COMPENSATE FOR TIMING SKEW AND OPERATION METHOD THEREOF 有权

    公开(公告)号：US20220247438A1

    公开(公告)日：2022-08-04

    申请号：US17490563

    申请日：2021-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： CHANGKYU SEOL ,  BYUNG-SUK WOO ,  Sucheol LEE

    IPC: H04B1/10 ,  H04B1/00 ,  H04B17/29 ,  H04B17/21

    Abstract: An electronic circuit converts a receive signal being analog into reception data being digital. The electronic circuit includes a delay circuit that receives a first receive signal and outputs a reference signal, the reference signal being generated by delaying the first receive signal as much as one of a plurality of different timing delays respectively set to a plurality of loops, a sampler that receives a second receive signal and samples the second receive signal based on the reference signal in each of the plurality of loops, a timing skew estimation circuit that outputs a compensation signal for compensating for a timing skew by extracting a statistical characteristic of a plurality of sample data sampled through the sampler and estimating the timing skew based on the statistical characteristic, and a controller that controls an operation of the timing skew estimation circuit.

    RECEIVERS FOR PERFORMING REFERENCE VOLTAGE TRAINING AND MEMORY SYSTEMS INCLUDING THE SAME
    4.
    发明申请
    RECEIVERS FOR PERFORMING REFERENCE VOLTAGE TRAINING AND MEMORY SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20220199126A1

    公开(公告)日：2022-06-23

    申请号：US17377654

    申请日：2021-07-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sucheol LEE ,  Changkyu SEOL ,  Byungsuk WOO

    IPC: G11C5/14 ,  G11C11/4074

    Abstract: A receiver including: a data processing circuit, in a training mode, to compare a multi-level signal with first and second voltage signals, and to generate data density signals; a counter circuit to count the data density signals to generate counting values; a control circuit to store, in a register set, a voltage range, counting values corresponding to the voltage range and a control code associated with a first level of the first voltage signal and a second level of the second voltage signal, the voltage range being based on the first and second voltage signals; and a voltage generation circuit, in the training mode, to apply the first and second voltage signals to the data processing circuit and to increase the first level and the second level by a difference between the first and second control signals in response to the control code from the control circuit.

Patent Agency Ranking