公开(公告)号：US20140043896A1

公开(公告)日：2014-02-13

申请号：US13939611

申请日：2013-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Weon-Ho Park ,  Hyok-Ki Kwon ,  Min-Sup Kim ,  Min-Su Kim ,  Byoung-Ho Kim ,  Eui-Yeol Kim ,  Sang-Hoon Park ,  Ji-Hoon Park ,  Min-Jee Sung ,  Hyo-Soung Sim ,  Chang-Min Jeon ,  Hee-Seog Jeon

IPC: G11C16/34

CPC classification number: G11C16/3431 ,  G11C16/3427

Abstract: A method of preventing program-disturbances for a non-volatile semiconductor memory device having a plurality of memory cells of which each includes a selection transistor and a memory transistor coupled in series between a bit-line and a common source-line is provided. First non-selected memory cells that share a first selection-line with a selected memory cell, and second non-selected memory cells that do not share the first selection-line with the selected memory cell are determined when the selected memory cell is selected to be programmed among the memory cells. A negative voltage is applied to second selection-lines that are coupled to the second non-selected memory cells when the selected memory cell is programmed by applying a positive voltage to the first selection-line that is coupled to the selected memory cell.

Abstract translation: 提供一种防止具有多个存储单元的非易失性半导体存储器件的程序干扰的方法，每个存储单元中的每一个包括选择晶体管和串联耦合在位线和公共源极线之间的存储晶体管。 当选择的存储器单元被选择为为了选择存储单元时，与所选存储单元共享第一选择行的第一非选择存储单元和不与所选存储单元共享第一选择行的第二未选择存储单元 在存储单元之间进行编程。 当所选择的存储单元通过向耦合到所选存储单元的第一选择线施加正电压来编程时，将负电压施加到耦合到第二未选择存储单元的第二选择线。

公开(公告)号：US20140217490A1

公开(公告)日：2014-08-07

申请号：US13803791

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bo-Young Seo ,  Weon-Ho Park ,  Chang-Min Jeon ,  Yong-Sang Cho

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

Abstract: In a nonvolatile memory device and a method for fabricating the same, a device comprises a substrate, a trench in the substrate and a first gate pattern comprising a first bottom gate electrode having a first portion in the trench and having a second portion on the first portion and protruding in an upward direction relative to an upper surface of the substrate. A second gate pattern comprising a second gate electrode is on the substrate at a side of the first gate pattern and insulated from the first gate pattern. An impurity region is present in the substrate at a side of the first gate pattern opposite the second gate pattern, and overlapping part of the trench.

Abstract translation: 在非易失性存储器件及其制造方法中，器件包括衬底，衬底中的沟槽和第一栅极图案，第一栅极图案包括第一底部栅极电极，第一底部栅电极在沟槽中具有第一部分，并且在第一 并相对于基板的上表面向上方突出。 包括第二栅电极的第二栅极图案在第一栅极图案的一侧的基板上，并与第一栅极图案绝缘。 在第一栅极图案的与第二栅极图案相对的一侧上存在杂质区域和沟槽的重叠部分。