公开(公告)号：US09734276B2

公开(公告)日：2017-08-15

申请号：US14875910

申请日：2015-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-tae Kim ,  Chang-beom Kim

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/118

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  H01L27/0207 ,  H01L27/11807

Abstract: A method of designing a layout of an integrated circuit (IC) includes: preparing a standard cell library that stores a first standard cell and a second standard cell, each of the first standard cell and the second standard cell including a plurality of conductive lines that extend in a first direction, placing the first standard cell and the second standard cell to be adjacent to each other in a first boundary parallel to the plurality of conductive lines, and generating a decoupling capacitor by using at least one first conductive line of the plurality of conductive lines when a same voltage is applied to a first pattern adjacent to the first boundary in the first standard cell and a second pattern adjacent to the first boundary in the second standard cell, the at least one first conductive line being adjacent to the first boundary.

公开(公告)号：US11189639B2

公开(公告)日：2021-11-30

申请号：US16842867

申请日：2020-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-young Kim ,  Chang-beom Kim ,  Hyun-jeong Roh ,  Tae-joong Song ,  Dal-hee Lee ,  Sung-we Cho

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

公开(公告)号：US10651201B2

公开(公告)日：2020-05-12

申请号：US15913530

申请日：2018-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-young Kim ,  Chang-beom Kim ,  Hyun-jeong Roh ,  Tae-joong Song ,  Dal-hee Lee ,  Sung-we Cho

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

公开(公告)号：US20200235126A1

公开(公告)日：2020-07-23

申请号：US16842867

申请日：2020-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-young KIM ,  Chang-beom Kim ,  Hyun-jeong Roh ,  Tae-joong Song ,  Dal-hee Lee ,  Sung-we Cho

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.