公开(公告)号：US10649904B2

公开(公告)日：2020-05-12

申请号：US15422442

申请日：2017-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hao Wang ,  Dilip Muthukrishnan ,  Brian C. Grayson

IPC: G06F12/0875 ,  G06F12/0888 ,  G06F12/0897

Abstract: According to one general aspect, an apparatus may include a load/store circuit and a region size detection circuit. The load/store circuit may be configured to issue a plurality of store instructions to store data in a memory system. The region size detection circuit may be configured to determine a cache from a plurality of caches to store a stream of store instructions based upon, at least in part, by tracking multiple cache-line address entries in the plurality of store instructions, wherein each address entry is updated at a different frequency.