公开(公告)号：US20250166692A1

公开(公告)日：2025-05-22

申请号：US18748051

申请日：2024-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hyun PARK ,  Dong Woo BAEK ,  Hyeung Joon CHA

IPC: G11C11/4078 ,  G11C11/4074 ,  H02H7/00

Abstract: A power management integrated circuit includes an internal output transistor connected to an external voltage input line, to which an external voltage is supplied, and outputting an internal output voltage, a self-overvoltage protection circuit detecting whether the external voltage exceeds a breakdown condition for the internal output transistor and providing a gate voltage to a gate terminal of the internal output transistor and a clamp circuit outputting, as the internal output voltage, a first clamp voltage having a uniform level in a first overvoltage clamp mode and a second clamp voltage, which is leveled down from the external voltage, in a second overvoltage clamp mode. When the internal output transistor is turned off, the clamp circuit outputs the internal output voltage. The external voltage in the second overvoltage clamp mode may be greater than the external voltage in the first overvoltage clamp mode.