公开(公告)号：US20240339450A1

公开(公告)日：2024-10-10

申请号：US18746928

申请日：2024-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggil YANG ,  Minju KIM ,  Donghyi KOH

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/7851

Abstract: An integrated circuit device including a substrate including first and second device regions; a first fin active region on the first device region; a second fin active region on the second device region; an isolation film covering side walls of the active regions; gate cut insulating patterns on the isolation film on the device regions; a gate line extending on the fin active regions, the gate line having a length limited by the gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the fin active regions and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom to the top surface.

公开(公告)号：US20230335552A1

公开(公告)日：2023-10-19

申请号：US18212304

申请日：2023-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggil YANG ,  Minju KIM ,  Donghyi KOH

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/7851

Abstract: An integrated circuit device including a substrate including first and second device regions; a first fin active region on the first device region; a second fin active region on the second device region; an isolation film covering side walls of the active regions; gate cut insulating patterns on the isolation film on the device regions; a gate line extending on the fin active regions, the gate line having a length limited by the gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the fin active regions and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom to the top surface.

公开(公告)号：US20220173097A1

公开(公告)日：2022-06-02

申请号：US17372896

申请日：2021-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggil YANG ,  Minju KIM ,  Donghyi KOH

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06

Abstract: An integrated circuit device including a substrate including first and second device regions; a first fin active region on the first device region; a second fin active region on the second device region; an isolation film covering side walls of the active regions; gate cut insulating patterns on the isolation film on the device regions; a gate line extending on the fin active regions, the gate line having a length limited by the gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the fin active regions and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom to the top surface.